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📄 yiweijcq.tan.qmsg

📁 是一些很好的FPGA设计实例
💻 QMSG
📖 第 1 页 / 共 3 页
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123 
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 3 -1 0 } } { "d:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "d:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register a b 250.0 MHz Internal " "Info: Clock clk Internal fmax is restricted to 250.0 MHz between source register a and destination register b" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.0 ns 2.0 ns 4.0 ns " "Info: fmax restricted to Clock High delay (2.0 ns) plus Clock Low delay (2.0 ns) : restricted to 4.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.500 ns + Longest register register " "Info: + Longest register to register delay is 0.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns a 1 REG LC4_C4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_C4; Fanout = 1; REG Node = 'a'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "" { a } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.400 ns) 0.500 ns b 2 REG LC3_C4 1 " "Info: 2: + IC(0.100 ns) + CELL(0.400 ns) = 0.500 ns; Loc. = LC3_C4; Fanout = 1; REG Node = 'b'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "0.500 ns" { a b } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.400 ns 80.00 % " "Info: Total cell delay = 0.400 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.100 ns 20.00 % " "Info: Total interconnect delay = 0.100 ns ( 20.00 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "0.500 ns" { a b } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_39 4 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns b 2 REG LC3_C4 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC3_C4; Fanout = 1; REG Node = 'b'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "0.200 ns" { clk b } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.500 ns" { clk b } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_39 4 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns a 2 REG LC4_C4 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4_C4; Fanout = 1; REG Node = 'a'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "0.200 ns" { clk a } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.500 ns" { clk a } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.500 ns" { clk b } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.500 ns" { clk a } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "0.500 ns" { a b } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.500 ns" { clk b } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.500 ns" { clk a } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "" { b } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "a din clk 0.600 ns register " "Info: tsu for register a (data pin = din, clock pin = clk) is 0.600 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.700 ns + Longest pin register " "Info: + Longest pin to register delay is 1.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns din 1 PIN PIN_91 1 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_91; Fanout = 1; PIN Node = 'din'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "" { din } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 1.700 ns a 2 REG LC4_C4 1 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 1.700 ns; Loc. = LC4_C4; Fanout = 1; REG Node = 'a'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "0.400 ns" { din a } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.700 ns 100.00 % " "Info: Total cell delay = 1.700 ns ( 100.00 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.700 ns" { din a } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_39 4 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns a 2 REG LC4_C4 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4_C4; Fanout = 1; REG Node = 'a'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "0.200 ns" { clk a } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.500 ns" { clk a } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.700 ns" { din a } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.500 ns" { clk a } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout dout~reg0 6.200 ns register " "Info: tco from clock clk to destination pin dout through register dout~reg0 is 6.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_39 4 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns dout~reg0 2 REG LC2_C4 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2_C4; Fanout = 1; REG Node = 'dout~reg0'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "0.200 ns" { clk dout~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.500 ns" { clk dout~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.400 ns + Longest register pin " "Info: + Longest register to pin delay is 4.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dout~reg0 1 REG LC2_C4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_C4; Fanout = 1; REG Node = 'dout~reg0'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "" { dout~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(3.800 ns) 4.400 ns dout 2 PIN PIN_57 0 " "Info: 2: + IC(0.600 ns) + CELL(3.800 ns) = 4.400 ns; Loc. = PIN_57; Fanout = 0; PIN Node = 'dout'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "4.400 ns" { dout~reg0 dout } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 86.36 % " "Info: Total cell delay = 3.800 ns ( 86.36 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns 13.64 % " "Info: Total interconnect delay = 0.600 ns ( 13.64 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "4.400 ns" { dout~reg0 dout } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.500 ns" { clk dout~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "4.400 ns" { dout~reg0 dout } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "a din clk 0.500 ns register " "Info: th for register a (data pin = din, clock pin = clk) is 0.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_39 4 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns a 2 REG LC4_C4 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC4_C4; Fanout = 1; REG Node = 'a'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "0.200 ns" { clk a } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.500 ns" { clk a } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.700 ns + " "Info: + Micro hold delay of destination is 0.700 ns" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.700 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns din 1 PIN PIN_91 1 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_91; Fanout = 1; PIN Node = 'din'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "" { din } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 1.700 ns a 2 REG LC4_C4 1 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 1.700 ns; Loc. = LC4_C4; Fanout = 1; REG Node = 'a'" {  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "0.400 ns" { din a } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" "" "" { Text "d:/vhdl数字逻辑教程/7.8移位寄存器#1/yiweijcq.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.700 ns 100.00 % " "Info: Total cell delay = 1.700 ns ( 100.00 % )" {  } {  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.700 ns" { din a } "NODE_NAME" } } }  } 0}  } { { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.500 ns" { clk a } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq_cmp.qrpt" Compiler "yiweijcq" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/7.8移位寄存器#1/db/yiweijcq.quartus_db" { Floorplan "" "" "1.700 ns" { din a } "NODE_NAME" } } }  } 0}
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