luojidanyuan.map.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 15 17:27:54 2007 " "Info: Processing started: Tue May 15 17:27:54 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off luojidanyuan -c luojidanyuan " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off luojidanyuan -c luojidanyuan" {  } {  } 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"when\" luojidanyuan.vhd(17) " "Error: VHDL syntax error at luojidanyuan.vhd(17) near text \"when\"" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 17 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"select\"; expecting \"'\" or \"(\" or \".\" luojidanyuan.vhd(17) " "Error: VHDL syntax error at luojidanyuan.vhd(17) near text \"select\"; expecting \"'\" or \"(\" or \".\"" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 17 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_STRING_TYPE_MISMATCH" "boolean luojidanyuan.vhd(18) " "Error: VHDL type mismatch error at luojidanyuan.vhd(18): boolean type does not match string literal" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 18 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\",\"; expecting \";\" luojidanyuan.vhd(18) " "Error: VHDL syntax error at luojidanyuan.vhd(18) near text \",\"; expecting \";\"" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 18 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_STRING_TYPE_MISMATCH" "boolean luojidanyuan.vhd(19) " "Error: VHDL type mismatch error at luojidanyuan.vhd(19): boolean type does not match string literal" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 19 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\",\"; expecting \";\" luojidanyuan.vhd(19) " "Error: VHDL syntax error at luojidanyuan.vhd(19) near text \",\"; expecting \";\"" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 19 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_STRING_TYPE_MISMATCH" "boolean luojidanyuan.vhd(20) " "Error: VHDL type mismatch error at luojidanyuan.vhd(20): boolean type does not match string literal" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 20 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\",\"; expecting \";\" luojidanyuan.vhd(20) " "Error: VHDL syntax error at luojidanyuan.vhd(20) near text \",\"; expecting \";\"" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 20 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_STRING_TYPE_MISMATCH" "boolean luojidanyuan.vhd(21) " "Error: VHDL type mismatch error at luojidanyuan.vhd(21): boolean type does not match string literal" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 21 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\",\"; expecting \";\" luojidanyuan.vhd(21) " "Error: VHDL syntax error at luojidanyuan.vhd(21) near text \",\"; expecting \";\"" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 21 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_STRING_TYPE_MISMATCH" "boolean luojidanyuan.vhd(22) " "Error: VHDL type mismatch error at luojidanyuan.vhd(22): boolean type does not match string literal" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 22 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\",\"; expecting \";\" luojidanyuan.vhd(22) " "Error: VHDL syntax error at luojidanyuan.vhd(22) near text \",\"; expecting \";\"" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 22 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_STRING_TYPE_MISMATCH" "boolean luojidanyuan.vhd(23) " "Error: VHDL type mismatch error at luojidanyuan.vhd(23): boolean type does not match string literal" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 23 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\",\"; expecting \";\" luojidanyuan.vhd(23) " "Error: VHDL syntax error at luojidanyuan.vhd(23) near text \",\"; expecting \";\"" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 23 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_STRING_TYPE_MISMATCH" "boolean luojidanyuan.vhd(24) " "Error: VHDL type mismatch error at luojidanyuan.vhd(24): boolean type does not match string literal" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 24 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\",\"; expecting \";\" luojidanyuan.vhd(24) " "Error: VHDL syntax error at luojidanyuan.vhd(24) near text \",\"; expecting \";\"" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 24 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"others\" luojidanyuan.vhd(25) " "Error: VHDL syntax error at luojidanyuan.vhd(25) near text \"others\"" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 25 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"select\"; expecting \"'\" or \"(\" or \".\" luojidanyuan.vhd(27) " "Error: VHDL syntax error at luojidanyuan.vhd(27) near text \"select\"; expecting \"'\" or \"(\" or \".\"" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 27 0 0 } }  } 0}
{ "Error" "EVRFX_VHDL_STRING_TYPE_MISMATCH" "boolean luojidanyuan.vhd(28) " "Error: VHDL type mismatch error at luojidanyuan.vhd(28): boolean type does not match string literal" {  } { { "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.5算术逻辑单元/luojidanyuan.vhd" 28 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "luojidanyuan.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file luojidanyuan.vhd" {  } {  } 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 19 s 0 s " "Error: Quartus II Analysis & Synthesis was unsuccessful. 19 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Tue May 15 17:27:56 2007 " "Error: Processing ended: Tue May 15 17:27:56 2007" {  } {  } 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}