📄 cufaqi.tan.qmsg
字号:
{ "Info" "ITDB_TSU_RESULT" "q~reg0 d clk 1.100 ns register " "Info: tsu for register q~reg0 (data pin = d, clock pin = clk) is 1.100 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.200 ns + Longest pin register " "Info: + Longest pin to register delay is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns d 1 PIN PIN_91 1 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_91; Fanout = 1; PIN Node = 'd'" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "" { d } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.600 ns) 2.200 ns q~reg0 2 REG LC2_A17 1 " "Info: 2: + IC(0.300 ns) + CELL(0.600 ns) = 2.200 ns; Loc. = LC2_A17; Fanout = 1; REG Node = 'q~reg0'" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "0.900 ns" { d q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 86.36 % " "Info: Total cell delay = 1.900 ns ( 86.36 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns 13.64 % " "Info: Total interconnect delay = 0.300 ns ( 13.64 % )" { } { } 0} } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "2.200 ns" { d q~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.400 ns + " "Info: + Micro setup delay of destination is 0.400 ns" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_39 1 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 1; CLK Node = 'clk'" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns q~reg0 2 REG LC2_A17 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2_A17; Fanout = 1; REG Node = 'q~reg0'" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "0.200 ns" { clk q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" { } { } 0} } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk q~reg0 } "NODE_NAME" } } } } 0} } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "2.200 ns" { d q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk q~reg0 } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk q q~reg0 6.100 ns register " "Info: tco from clock clk to destination pin q through register q~reg0 is 6.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_39 1 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 1; CLK Node = 'clk'" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns q~reg0 2 REG LC2_A17 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2_A17; Fanout = 1; REG Node = 'q~reg0'" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "0.200 ns" { clk q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" { } { } 0} } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk q~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.300 ns + Longest register pin " "Info: + Longest register to pin delay is 4.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q~reg0 1 REG LC2_A17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_A17; Fanout = 1; REG Node = 'q~reg0'" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "" { q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(3.800 ns) 4.300 ns q 2 PIN PIN_6 0 " "Info: 2: + IC(0.500 ns) + CELL(3.800 ns) = 4.300 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'q'" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "4.300 ns" { q~reg0 q } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 88.37 % " "Info: Total cell delay = 3.800 ns ( 88.37 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.500 ns 11.63 % " "Info: Total interconnect delay = 0.500 ns ( 11.63 % )" { } { } 0} } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "4.300 ns" { q~reg0 q } "NODE_NAME" } } } } 0} } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "4.300 ns" { q~reg0 q } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TH_RESULT" "q~reg0 rst clk 0.200 ns register " "Info: th for register q~reg0 (data pin = rst, clock pin = clk) is 0.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.500 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_39 1 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 1; CLK Node = 'clk'" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns q~reg0 2 REG LC2_A17 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2_A17; Fanout = 1; REG Node = 'q~reg0'" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "0.200 ns" { clk q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" { } { } 0} } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk q~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.700 ns + " "Info: + Micro hold delay of destination is 0.700 ns" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns rst 1 PIN PIN_89 1 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_89; Fanout = 1; PIN Node = 'rst'" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "" { rst } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.400 ns) 2.000 ns q~reg0 2 REG LC2_A17 1 " "Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.000 ns; Loc. = LC2_A17; Fanout = 1; REG Node = 'q~reg0'" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "0.700 ns" { rst q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.700 ns 85.00 % " "Info: Total cell delay = 1.700 ns ( 85.00 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns 15.00 % " "Info: Total interconnect delay = 0.300 ns ( 15.00 % )" { } { } 0} } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "2.000 ns" { rst q~reg0 } "NODE_NAME" } } } } 0} } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "2.000 ns" { rst q~reg0 } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk q q~reg0 6.100 ns register " "Info: Minimum tco from clock clk to destination pin q through register q~reg0 is 6.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.500 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 1.300 ns clk 1 CLK PIN_39 1 " "Info: 1: + IC(0.000 ns) + CELL(1.300 ns) = 1.300 ns; Loc. = PIN_39; Fanout = 1; CLK Node = 'clk'" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 7 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 1.500 ns q~reg0 2 REG LC2_A17 1 " "Info: 2: + IC(0.200 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC2_A17; Fanout = 1; REG Node = 'q~reg0'" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "0.200 ns" { clk q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 86.67 % " "Info: Total cell delay = 1.300 ns ( 86.67 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 13.33 % " "Info: Total interconnect delay = 0.200 ns ( 13.33 % )" { } { } 0} } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk q~reg0 } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.300 ns + " "Info: + Micro clock to output delay of source is 0.300 ns" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.300 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns q~reg0 1 REG LC2_A17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_A17; Fanout = 1; REG Node = 'q~reg0'" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "" { q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(3.800 ns) 4.300 ns q 2 PIN PIN_6 0 " "Info: 2: + IC(0.500 ns) + CELL(3.800 ns) = 4.300 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'q'" { } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "4.300 ns" { q~reg0 q } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" "" "" { Text "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/cufaqi.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 88.37 % " "Info: Total cell delay = 3.800 ns ( 88.37 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.500 ns 11.63 % " "Info: Total interconnect delay = 0.500 ns ( 11.63 % )" { } { } 0} } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "4.300 ns" { q~reg0 q } "NODE_NAME" } } } } 0} } { { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "1.500 ns" { clk q~reg0 } "NODE_NAME" } } } { "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" "" "" { Report "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi_cmp.qrpt" Compiler "cufaqi" "UNKNOWN" "V1" "d:/vhdl数字逻辑教程/5.8用guarded block实现d触发器/db/cufaqi.quartus_db" { Floorplan "" "" "4.300 ns" { q~reg0 q } "NODE_NAME" } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 16 10:57:45 2007 " "Info: Processing ended: Wed May 16 10:57:45 2007" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0} } { } 0}
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