cdu24.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_TPD_RESULT" "sa co 10.071 ns Longest " "Info: Longest tpd from source pin \"sa\" to destination pin \"co\" is 10.071 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns sa 1 CLK PIN_T16 2 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_T16; Fanout = 2; CLK Node = 'sa'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sa } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.503 ns) + CELL(0.075 ns) 5.665 ns co~9 2 COMB LC_X8_Y18_N8 1 " "Info: 2: + IC(4.503 ns) + CELL(0.075 ns) = 5.665 ns; Loc. = LC_X8_Y18_N8; Fanout = 1; COMB Node = 'co~9'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.578 ns" { sa co~9 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.002 ns) + CELL(2.404 ns) 10.071 ns co 3 PIN PIN_Y15 0 " "Info: 3: + IC(2.002 ns) + CELL(2.404 ns) = 10.071 ns; Loc. = PIN_Y15; Fanout = 0; PIN Node = 'co'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.406 ns" { co~9 co } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.566 ns ( 35.41 % ) " "Info: Total cell delay = 3.566 ns ( 35.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.505 ns ( 64.59 % ) " "Info: Total interconnect delay = 6.505 ns ( 64.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.071 ns" { sa co~9 co } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.071 ns" { sa sa~out0 co~9 co } { 0.000ns 0.000ns 4.503ns 2.002ns } { 0.000ns 1.087ns 0.075ns 2.404ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 10 22:47:13 2007 " "Info: Processing ended: Wed Oct 10 22:47:13 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}