cdu24.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sa register out1\[1\] register out2\[3\] 383.58 MHz 2.607 ns Internal " "Info: Clock \"sa\" has Internal fmax of 383.58 MHz between source register \"out1\[1\]\" and destination register \"out2\[3\]\" (period= 2.607 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.441 ns + Longest register register " "Info: + Longest register to register delay is 2.441 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns out1\[1\] 1 REG LC_X9_Y18_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y18_N8; Fanout = 4; REG Node = 'out1\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { out1[1] } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.398 ns) + CELL(0.366 ns) 0.764 ns process0~54 2 COMB LC_X9_Y18_N6 1 " "Info: 2: + IC(0.398 ns) + CELL(0.366 ns) = 0.764 ns; Loc. = LC_X9_Y18_N6; Fanout = 1; COMB Node = 'process0~54'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.764 ns" { out1[1] process0~54 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.324 ns) + CELL(0.075 ns) 1.163 ns process0~1 3 COMB LC_X9_Y18_N5 4 " "Info: 3: + IC(0.324 ns) + CELL(0.075 ns) = 1.163 ns; Loc. = LC_X9_Y18_N5; Fanout = 4; COMB Node = 'process0~1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.399 ns" { process0~54 process0~1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.320 ns) + CELL(0.341 ns) 1.824 ns out2\[0\]~52COUT1_57 4 COMB LC_X9_Y18_N1 2 " "Info: 4: + IC(0.320 ns) + CELL(0.341 ns) = 1.824 ns; Loc. = LC_X9_Y18_N1; Fanout = 2; COMB Node = 'out2\[0\]~52COUT1_57'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.661 ns" { process0~1 out2[0]~52COUT1_57 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 1.884 ns out2\[1\]~53COUT1 5 COMB LC_X9_Y18_N2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 1.884 ns; Loc. = LC_X9_Y18_N2; Fanout = 2; COMB Node = 'out2\[1\]~53COUT1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.060 ns" { out2[0]~52COUT1_57 out2[1]~53COUT1 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 1.944 ns out2\[2\]~54COUT1_58 6 COMB LC_X9_Y18_N3 1 " "Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 1.944 ns; Loc. = LC_X9_Y18_N3; Fanout = 1; COMB Node = 'out2\[2\]~54COUT1_58'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.060 ns" { out2[1]~53COUT1 out2[2]~54COUT1_58 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.497 ns) 2.441 ns out2\[3\] 7 REG LC_X9_Y18_N4 4 " "Info: 7: + IC(0.000 ns) + CELL(0.497 ns) = 2.441 ns; Loc. = LC_X9_Y18_N4; Fanout = 4; REG Node = 'out2\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.497 ns" { out2[2]~54COUT1_58 out2[3] } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.399 ns ( 57.31 % ) " "Info: Total cell delay = 1.399 ns ( 57.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.042 ns ( 42.69 % ) " "Info: Total interconnect delay = 1.042 ns ( 42.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.441 ns" { out1[1] process0~54 process0~1 out2[0]~52COUT1_57 out2[1]~53COUT1 out2[2]~54COUT1_58 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.441 ns" { out1[1] process0~54 process0~1 out2[0]~52COUT1_57 out2[1]~53COUT1 out2[2]~54COUT1_58 out2[3] } { 0.000ns 0.398ns 0.324ns 0.320ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.366ns 0.075ns 0.341ns 0.060ns 0.060ns 0.497ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sa destination 7.268 ns + Shortest register " "Info: + Shortest clock path from clock \"sa\" to destination register is 7.268 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns sa 1 CLK PIN_T16 2 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_T16; Fanout = 2; CLK Node = 'sa'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sa } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.790 ns) + CELL(0.183 ns) 3.060 ns clk~7 2 COMB LC_X8_Y18_N4 9 " "Info: 2: + IC(1.790 ns) + CELL(0.183 ns) = 3.060 ns; Loc. = LC_X8_Y18_N4; Fanout = 9; COMB Node = 'clk~7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.973 ns" { sa clk~7 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.666 ns) + CELL(0.542 ns) 7.268 ns out2\[3\] 3 REG LC_X9_Y18_N4 4 " "Info: 3: + IC(3.666 ns) + CELL(0.542 ns) = 7.268 ns; Loc. = LC_X9_Y18_N4; Fanout = 4; REG Node = 'out2\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.208 ns" { clk~7 out2[3] } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.812 ns ( 24.93 % ) " "Info: Total cell delay = 1.812 ns ( 24.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.456 ns ( 75.07 % ) " "Info: Total interconnect delay = 5.456 ns ( 75.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.268 ns" { sa clk~7 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.268 ns" { sa sa~out0 clk~7 out2[3] } { 0.000ns 0.000ns 1.790ns 3.666ns } { 0.000ns 1.087ns 0.183ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sa source 7.268 ns - Longest register " "Info: - Longest clock path from clock \"sa\" to source register is 7.268 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns sa 1 CLK PIN_T16 2 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_T16; Fanout = 2; CLK Node = 'sa'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sa } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.790 ns) + CELL(0.183 ns) 3.060 ns clk~7 2 COMB LC_X8_Y18_N4 9 " "Info: 2: + IC(1.790 ns) + CELL(0.183 ns) = 3.060 ns; Loc. = LC_X8_Y18_N4; Fanout = 9; COMB Node = 'clk~7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.973 ns" { sa clk~7 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.666 ns) + CELL(0.542 ns) 7.268 ns out1\[1\] 3 REG LC_X9_Y18_N8 4 " "Info: 3: + IC(3.666 ns) + CELL(0.542 ns) = 7.268 ns; Loc. = LC_X9_Y18_N8; Fanout = 4; REG Node = 'out1\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.208 ns" { clk~7 out1[1] } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.812 ns ( 24.93 % ) " "Info: Total cell delay = 1.812 ns ( 24.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.456 ns ( 75.07 % ) " "Info: Total interconnect delay = 5.456 ns ( 75.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.268 ns" { sa clk~7 out1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.268 ns" { sa sa~out0 clk~7 out1[1] } { 0.000ns 0.000ns 1.790ns 3.666ns } { 0.000ns 1.087ns 0.183ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.268 ns" { sa clk~7 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.268 ns" { sa sa~out0 clk~7 out2[3] } { 0.000ns 0.000ns 1.790ns 3.666ns } { 0.000ns 1.087ns 0.183ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.268 ns" { sa clk~7 out1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.268 ns" { sa sa~out0 clk~7 out1[1] } { 0.000ns 0.000ns 1.790ns 3.666ns } { 0.000ns 1.087ns 0.183ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.441 ns" { out1[1] process0~54 process0~1 out2[0]~52COUT1_57 out2[1]~53COUT1 out2[2]~54COUT1_58 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.441 ns" { out1[1] process0~54 process0~1 out2[0]~52COUT1_57 out2[1]~53COUT1 out2[2]~54COUT1_58 out2[3] } { 0.000ns 0.398ns 0.324ns 0.320ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.366ns 0.075ns 0.341ns 0.060ns 0.060ns 0.497ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.268 ns" { sa clk~7 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.268 ns" { sa sa~out0 clk~7 out2[3] } { 0.000ns 0.000ns 1.790ns 3.666ns } { 0.000ns 1.087ns 0.183ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.268 ns" { sa clk~7 out1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.268 ns" { sa sa~out0 clk~7 out1[1] } { 0.000ns 0.000ns 1.790ns 3.666ns } { 0.000ns 1.087ns 0.183ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk2 register out1\[1\] register out2\[3\] 383.58 MHz 2.607 ns Internal " "Info: Clock \"clk2\" has Internal fmax of 383.58 MHz between source register \"out1\[1\]\" and destination register \"out2\[3\]\" (period= 2.607 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.441 ns + Longest register register " "Info: + Longest register to register delay is 2.441 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns out1\[1\] 1 REG LC_X9_Y18_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y18_N8; Fanout = 4; REG Node = 'out1\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { out1[1] } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.398 ns) + CELL(0.366 ns) 0.764 ns process0~54 2 COMB LC_X9_Y18_N6 1 " "Info: 2: + IC(0.398 ns) + CELL(0.366 ns) = 0.764 ns; Loc. = LC_X9_Y18_N6; Fanout = 1; COMB Node = 'process0~54'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.764 ns" { out1[1] process0~54 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.324 ns) + CELL(0.075 ns) 1.163 ns process0~1 3 COMB LC_X9_Y18_N5 4 " "Info: 3: + IC(0.324 ns) + CELL(0.075 ns) = 1.163 ns; Loc. = LC_X9_Y18_N5; Fanout = 4; COMB Node = 'process0~1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.399 ns" { process0~54 process0~1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.320 ns) + CELL(0.341 ns) 1.824 ns out2\[0\]~52COUT1_57 4 COMB LC_X9_Y18_N1 2 " "Info: 4: + IC(0.320 ns) + CELL(0.341 ns) = 1.824 ns; Loc. = LC_X9_Y18_N1; Fanout = 2; COMB Node = 'out2\[0\]~52COUT1_57'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.661 ns" { process0~1 out2[0]~52COUT1_57 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 1.884 ns out2\[1\]~53COUT1 5 COMB LC_X9_Y18_N2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 1.884 ns; Loc. = LC_X9_Y18_N2; Fanout = 2; COMB Node = 'out2\[1\]~53COUT1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.060 ns" { out2[0]~52COUT1_57 out2[1]~53COUT1 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 1.944 ns out2\[2\]~54COUT1_58 6 COMB LC_X9_Y18_N3 1 " "Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 1.944 ns; Loc. = LC_X9_Y18_N3; Fanout = 1; COMB Node = 'out2\[2\]~54COUT1_58'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.060 ns" { out2[1]~53COUT1 out2[2]~54COUT1_58 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.497 ns) 2.441 ns out2\[3\] 7 REG LC_X9_Y18_N4 4 " "Info: 7: + IC(0.000 ns) + CELL(0.497 ns) = 2.441 ns; Loc. = LC_X9_Y18_N4; Fanout = 4; REG Node = 'out2\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.497 ns" { out2[2]~54COUT1_58 out2[3] } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.399 ns ( 57.31 % ) " "Info: Total cell delay = 1.399 ns ( 57.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.042 ns ( 42.69 % ) " "Info: Total interconnect delay = 1.042 ns ( 42.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.441 ns" { out1[1] process0~54 process0~1 out2[0]~52COUT1_57 out2[1]~53COUT1 out2[2]~54COUT1_58 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.441 ns" { out1[1] process0~54 process0~1 out2[0]~52COUT1_57 out2[1]~53COUT1 out2[2]~54COUT1_58 out2[3] } { 0.000ns 0.398ns 0.324ns 0.320ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.366ns 0.075ns 0.341ns 0.060ns 0.060ns 0.497ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 destination 7.331 ns + Shortest register " "Info: + Shortest clock path from clock \"clk2\" to destination register is 7.331 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk2 1 CLK PIN_V17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_V17; Fanout = 1; CLK Node = 'clk2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.756 ns) + CELL(0.280 ns) 3.123 ns clk~7 2 COMB LC_X8_Y18_N4 9 " "Info: 2: + IC(1.756 ns) + CELL(0.280 ns) = 3.123 ns; Loc. = LC_X8_Y18_N4; Fanout = 9; COMB Node = 'clk~7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.036 ns" { clk2 clk~7 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.666 ns) + CELL(0.542 ns) 7.331 ns out2\[3\] 3 REG LC_X9_Y18_N4 4 " "Info: 3: + IC(3.666 ns) + CELL(0.542 ns) = 7.331 ns; Loc. = LC_X9_Y18_N4; Fanout = 4; REG Node = 'out2\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.208 ns" { clk~7 out2[3] } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.909 ns ( 26.04 % ) " "Info: Total cell delay = 1.909 ns ( 26.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.422 ns ( 73.96 % ) " "Info: Total interconnect delay = 5.422 ns ( 73.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.331 ns" { clk2 clk~7 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.331 ns" { clk2 clk2~out0 clk~7 out2[3] } { 0.000ns 0.000ns 1.756ns 3.666ns } { 0.000ns 1.087ns 0.280ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 source 7.331 ns - Longest register " "Info: - Longest clock path from clock \"clk2\" to source register is 7.331 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk2 1 CLK PIN_V17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_V17; Fanout = 1; CLK Node = 'clk2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.756 ns) + CELL(0.280 ns) 3.123 ns clk~7 2 COMB LC_X8_Y18_N4 9 " "Info: 2: + IC(1.756 ns) + CELL(0.280 ns) = 3.123 ns; Loc. = LC_X8_Y18_N4; Fanout = 9; COMB Node = 'clk~7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.036 ns" { clk2 clk~7 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.666 ns) + CELL(0.542 ns) 7.331 ns out1\[1\] 3 REG LC_X9_Y18_N8 4 " "Info: 3: + IC(3.666 ns) + CELL(0.542 ns) = 7.331 ns; Loc. = LC_X9_Y18_N8; Fanout = 4; REG Node = 'out1\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.208 ns" { clk~7 out1[1] } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.909 ns ( 26.04 % ) " "Info: Total cell delay = 1.909 ns ( 26.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.422 ns ( 73.96 % ) " "Info: Total interconnect delay = 5.422 ns ( 73.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.331 ns" { clk2 clk~7 out1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.331 ns" { clk2 clk2~out0 clk~7 out1[1] } { 0.000ns 0.000ns 1.756ns 3.666ns } { 0.000ns 1.087ns 0.280ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.331 ns" { clk2 clk~7 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.331 ns" { clk2 clk2~out0 clk~7 out2[3] } { 0.000ns 0.000ns 1.756ns 3.666ns } { 0.000ns 1.087ns 0.280ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.331 ns" { clk2 clk~7 out1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.331 ns" { clk2 clk2~out0 clk~7 out1[1] } { 0.000ns 0.000ns 1.756ns 3.666ns } { 0.000ns 1.087ns 0.280ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.441 ns" { out1[1] process0~54 process0~1 out2[0]~52COUT1_57 out2[1]~53COUT1 out2[2]~54COUT1_58 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.441 ns" { out1[1] process0~54 process0~1 out2[0]~52COUT1_57 out2[1]~53COUT1 out2[2]~54COUT1_58 out2[3] } { 0.000ns 0.398ns 0.324ns 0.320ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.366ns 0.075ns 0.341ns 0.060ns 0.060ns 0.497ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.331 ns" { clk2 clk~7 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.331 ns" { clk2 clk2~out0 clk~7 out2[3] } { 0.000ns 0.000ns 1.756ns 3.666ns } { 0.000ns 1.087ns 0.280ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.331 ns" { clk2 clk~7 out1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.331 ns" { clk2 clk2~out0 clk~7 out1[1] } { 0.000ns 0.000ns 1.756ns 3.666ns } { 0.000ns 1.087ns 0.280ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk2 co cay 12.559 ns register " "Info: tco from clock \"clk2\" to destination pin \"co\" through register \"cay\" is 12.559 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk2 source 7.331 ns + Longest register " "Info: + Longest clock path from clock \"clk2\" to source register is 7.331 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk2 1 CLK PIN_V17 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_V17; Fanout = 1; CLK Node = 'clk2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk2 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.756 ns) + CELL(0.280 ns) 3.123 ns clk~7 2 COMB LC_X8_Y18_N4 9 " "Info: 2: + IC(1.756 ns) + CELL(0.280 ns) = 3.123 ns; Loc. = LC_X8_Y18_N4; Fanout = 9; COMB Node = 'clk~7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.036 ns" { clk2 clk~7 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.666 ns) + CELL(0.542 ns) 7.331 ns cay 3 REG LC_X8_Y18_N6 1 " "Info: 3: + IC(3.666 ns) + CELL(0.542 ns) = 7.331 ns; Loc. = LC_X8_Y18_N6; Fanout = 1; REG Node = 'cay'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.208 ns" { clk~7 cay } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.909 ns ( 26.04 % ) " "Info: Total cell delay = 1.909 ns ( 26.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.422 ns ( 73.96 % ) " "Info: Total interconnect delay = 5.422 ns ( 73.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.331 ns" { clk2 clk~7 cay } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.331 ns" { clk2 clk2~out0 clk~7 cay } { 0.000ns 0.000ns 1.756ns 3.666ns } { 0.000ns 1.087ns 0.280ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.072 ns + Longest register pin " "Info: + Longest register to pin delay is 5.072 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cay 1 REG LC_X8_Y18_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y18_N6; Fanout = 1; REG Node = 'cay'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cay } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.386 ns) + CELL(0.280 ns) 0.666 ns co~9 2 COMB LC_X8_Y18_N8 1 " "Info: 2: + IC(0.386 ns) + CELL(0.280 ns) = 0.666 ns; Loc. = LC_X8_Y18_N8; Fanout = 1; COMB Node = 'co~9'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.666 ns" { cay co~9 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.002 ns) + CELL(2.404 ns) 5.072 ns co 3 PIN PIN_Y15 0 " "Info: 3: + IC(2.002 ns) + CELL(2.404 ns) = 5.072 ns; Loc. = PIN_Y15; Fanout = 0; PIN Node = 'co'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.406 ns" { co~9 co } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.684 ns ( 52.92 % ) " "Info: Total cell delay = 2.684 ns ( 52.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.388 ns ( 47.08 % ) " "Info: Total interconnect delay = 2.388 ns ( 47.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.072 ns" { cay co~9 co } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.072 ns" { cay co~9 co } { 0.000ns 0.386ns 2.002ns } { 0.000ns 0.280ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.331 ns" { clk2 clk~7 cay } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.331 ns" { clk2 clk2~out0 clk~7 cay } { 0.000ns 0.000ns 1.756ns 3.666ns } { 0.000ns 1.087ns 0.280ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.072 ns" { cay co~9 co } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.072 ns" { cay co~9 co } { 0.000ns 0.386ns 2.002ns } { 0.000ns 0.280ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}