cdu24.tan.qmsg

是一些很好的FPGA设计实例

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" {  } { { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 11 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "sa " "Info: Assuming node \"sa\" is an undefined clock" {  } { { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 11 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sa" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk2 " "Info: Assuming node \"clk2\" is an undefined clock" {  } { { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 11 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "clk~7 " "Info: Detected gated clock \"clk~7\" as buffer" {  } { { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 23 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk~7" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register out1\[1\] register out2\[3\] 383.58 MHz 2.607 ns Internal " "Info: Clock \"clk1\" has Internal fmax of 383.58 MHz between source register \"out1\[1\]\" and destination register \"out2\[3\]\" (period= 2.607 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.441 ns + Longest register register " "Info: + Longest register to register delay is 2.441 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns out1\[1\] 1 REG LC_X9_Y18_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y18_N8; Fanout = 4; REG Node = 'out1\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { out1[1] } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.398 ns) + CELL(0.366 ns) 0.764 ns process0~54 2 COMB LC_X9_Y18_N6 1 " "Info: 2: + IC(0.398 ns) + CELL(0.366 ns) = 0.764 ns; Loc. = LC_X9_Y18_N6; Fanout = 1; COMB Node = 'process0~54'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.764 ns" { out1[1] process0~54 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.324 ns) + CELL(0.075 ns) 1.163 ns process0~1 3 COMB LC_X9_Y18_N5 4 " "Info: 3: + IC(0.324 ns) + CELL(0.075 ns) = 1.163 ns; Loc. = LC_X9_Y18_N5; Fanout = 4; COMB Node = 'process0~1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.399 ns" { process0~54 process0~1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.320 ns) + CELL(0.341 ns) 1.824 ns out2\[0\]~52COUT1_57 4 COMB LC_X9_Y18_N1 2 " "Info: 4: + IC(0.320 ns) + CELL(0.341 ns) = 1.824 ns; Loc. = LC_X9_Y18_N1; Fanout = 2; COMB Node = 'out2\[0\]~52COUT1_57'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.661 ns" { process0~1 out2[0]~52COUT1_57 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 1.884 ns out2\[1\]~53COUT1 5 COMB LC_X9_Y18_N2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 1.884 ns; Loc. = LC_X9_Y18_N2; Fanout = 2; COMB Node = 'out2\[1\]~53COUT1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.060 ns" { out2[0]~52COUT1_57 out2[1]~53COUT1 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 1.944 ns out2\[2\]~54COUT1_58 6 COMB LC_X9_Y18_N3 1 " "Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 1.944 ns; Loc. = LC_X9_Y18_N3; Fanout = 1; COMB Node = 'out2\[2\]~54COUT1_58'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.060 ns" { out2[1]~53COUT1 out2[2]~54COUT1_58 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.497 ns) 2.441 ns out2\[3\] 7 REG LC_X9_Y18_N4 4 " "Info: 7: + IC(0.000 ns) + CELL(0.497 ns) = 2.441 ns; Loc. = LC_X9_Y18_N4; Fanout = 4; REG Node = 'out2\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.497 ns" { out2[2]~54COUT1_58 out2[3] } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.399 ns ( 57.31 % ) " "Info: Total cell delay = 1.399 ns ( 57.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.042 ns ( 42.69 % ) " "Info: Total interconnect delay = 1.042 ns ( 42.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.441 ns" { out1[1] process0~54 process0~1 out2[0]~52COUT1_57 out2[1]~53COUT1 out2[2]~54COUT1_58 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.441 ns" { out1[1] process0~54 process0~1 out2[0]~52COUT1_57 out2[1]~53COUT1 out2[2]~54COUT1_58 out2[3] } { 0.000ns 0.398ns 0.324ns 0.320ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.366ns 0.075ns 0.341ns 0.060ns 0.060ns 0.497ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 7.001 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1\" to destination register is 7.001 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk1 1 CLK PIN_U16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_U16; Fanout = 1; CLK Node = 'clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.631 ns) + CELL(0.075 ns) 2.793 ns clk~7 2 COMB LC_X8_Y18_N4 9 " "Info: 2: + IC(1.631 ns) + CELL(0.075 ns) = 2.793 ns; Loc. = LC_X8_Y18_N4; Fanout = 9; COMB Node = 'clk~7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.706 ns" { clk1 clk~7 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.666 ns) + CELL(0.542 ns) 7.001 ns out2\[3\] 3 REG LC_X9_Y18_N4 4 " "Info: 3: + IC(3.666 ns) + CELL(0.542 ns) = 7.001 ns; Loc. = LC_X9_Y18_N4; Fanout = 4; REG Node = 'out2\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.208 ns" { clk~7 out2[3] } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.704 ns ( 24.34 % ) " "Info: Total cell delay = 1.704 ns ( 24.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.297 ns ( 75.66 % ) " "Info: Total interconnect delay = 5.297 ns ( 75.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.001 ns" { clk1 clk~7 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.001 ns" { clk1 clk1~out0 clk~7 out2[3] } { 0.000ns 0.000ns 1.631ns 3.666ns } { 0.000ns 1.087ns 0.075ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 7.001 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 7.001 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns clk1 1 CLK PIN_U16 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_U16; Fanout = 1; CLK Node = 'clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.631 ns) + CELL(0.075 ns) 2.793 ns clk~7 2 COMB LC_X8_Y18_N4 9 " "Info: 2: + IC(1.631 ns) + CELL(0.075 ns) = 2.793 ns; Loc. = LC_X8_Y18_N4; Fanout = 9; COMB Node = 'clk~7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.706 ns" { clk1 clk~7 } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.666 ns) + CELL(0.542 ns) 7.001 ns out1\[1\] 3 REG LC_X9_Y18_N8 4 " "Info: 3: + IC(3.666 ns) + CELL(0.542 ns) = 7.001 ns; Loc. = LC_X9_Y18_N8; Fanout = 4; REG Node = 'out1\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.208 ns" { clk~7 out1[1] } "NODE_NAME" } } { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.704 ns ( 24.34 % ) " "Info: Total cell delay = 1.704 ns ( 24.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.297 ns ( 75.66 % ) " "Info: Total interconnect delay = 5.297 ns ( 75.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.001 ns" { clk1 clk~7 out1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.001 ns" { clk1 clk1~out0 clk~7 out1[1] } { 0.000ns 0.000ns 1.631ns 3.666ns } { 0.000ns 1.087ns 0.075ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.001 ns" { clk1 clk~7 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.001 ns" { clk1 clk1~out0 clk~7 out2[3] } { 0.000ns 0.000ns 1.631ns 3.666ns } { 0.000ns 1.087ns 0.075ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.001 ns" { clk1 clk~7 out1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.001 ns" { clk1 clk1~out0 clk~7 out1[1] } { 0.000ns 0.000ns 1.631ns 3.666ns } { 0.000ns 1.087ns 0.075ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "cdu24.vhd" "" { Text "E:/多功能数字钟的设计/cdu24/cdu24.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.441 ns" { out1[1] process0~54 process0~1 out2[0]~52COUT1_57 out2[1]~53COUT1 out2[2]~54COUT1_58 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.441 ns" { out1[1] process0~54 process0~1 out2[0]~52COUT1_57 out2[1]~53COUT1 out2[2]~54COUT1_58 out2[3] } { 0.000ns 0.398ns 0.324ns 0.320ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.366ns 0.075ns 0.341ns 0.060ns 0.060ns 0.497ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.001 ns" { clk1 clk~7 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.001 ns" { clk1 clk1~out0 clk~7 out2[3] } { 0.000ns 0.000ns 1.631ns 3.666ns } { 0.000ns 1.087ns 0.075ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.001 ns" { clk1 clk~7 out1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.001 ns" { clk1 clk1~out0 clk~7 out1[1] } { 0.000ns 0.000ns 1.631ns 3.666ns } { 0.000ns 1.087ns 0.075ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}