cdu60s.hier_info

是一些很好的FPGA设计实例

|cdu60s
clk1 => co~reg0.CLK
clk1 => out2[0].CLK
clk1 => out2[1].CLK
clk1 => out2[2].CLK
clk1 => out2[3].CLK
clk1 => out1[0].CLK
clk1 => out1[1].CLK
clk1 => out1[2].CLK
clk1 => out1[3].CLK
clr => out2[0].ACLR
clr => out2[1].ACLR
clr => out2[2].ACLR
clr => out2[3].ACLR
clr => out1[0].ACLR
clr => out1[1].ACLR
clr => out1[2].ACLR
clr => out1[3].ACLR
clr => co~reg0.ENA
co <= co~reg0.DB_MAX_OUTPUT_PORT_TYPE
m[0] <= out2[0].DB_MAX_OUTPUT_PORT_TYPE
m[1] <= out2[1].DB_MAX_OUTPUT_PORT_TYPE
m[2] <= out2[2].DB_MAX_OUTPUT_PORT_TYPE
m[3] <= out2[3].DB_MAX_OUTPUT_PORT_TYPE
m[4] <= comb~0.DB_MAX_OUTPUT_PORT_TYPE