📄 cdu60s.tan.qmsg
字号:
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk1 register out2\[3\] register out2\[3\] 367.78 MHz 2.719 ns Internal " "Info: Clock \"clk1\" has Internal fmax of 367.78 MHz between source register \"out2\[3\]\" and destination register \"out2\[3\]\" (period= 2.719 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.553 ns + Longest register register " "Info: + Longest register to register delay is 2.553 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns out2\[3\] 1 REG LC_X13_Y27_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y27_N8; Fanout = 4; REG Node = 'out2\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { out2[3] } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.410 ns) + CELL(0.366 ns) 0.776 ns Equal1~28 2 COMB LC_X13_Y27_N3 1 " "Info: 2: + IC(0.410 ns) + CELL(0.366 ns) = 0.776 ns; Loc. = LC_X13_Y27_N3; Fanout = 1; COMB Node = 'Equal1~28'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.776 ns" { out2[3] Equal1~28 } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.330 ns) + CELL(0.183 ns) 1.289 ns process0~1 3 COMB LC_X13_Y27_N1 6 " "Info: 3: + IC(0.330 ns) + CELL(0.183 ns) = 1.289 ns; Loc. = LC_X13_Y27_N1; Fanout = 6; COMB Node = 'process0~1'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.513 ns" { Equal1~28 process0~1 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.306 ns) + CELL(0.341 ns) 1.936 ns out2\[0\]~45COUT1_50 4 COMB LC_X13_Y27_N5 2 " "Info: 4: + IC(0.306 ns) + CELL(0.341 ns) = 1.936 ns; Loc. = LC_X13_Y27_N5; Fanout = 2; COMB Node = 'out2\[0\]~45COUT1_50'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.647 ns" { process0~1 out2[0]~45COUT1_50 } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 1.996 ns out2\[1\]~46COUT1 5 COMB LC_X13_Y27_N6 2 " "Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 1.996 ns; Loc. = LC_X13_Y27_N6; Fanout = 2; COMB Node = 'out2\[1\]~46COUT1'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.060 ns" { out2[0]~45COUT1_50 out2[1]~46COUT1 } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 2.056 ns out2\[2\]~47COUT1_51 6 COMB LC_X13_Y27_N7 1 " "Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 2.056 ns; Loc. = LC_X13_Y27_N7; Fanout = 1; COMB Node = 'out2\[2\]~47COUT1_51'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.060 ns" { out2[1]~46COUT1 out2[2]~47COUT1_51 } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.497 ns) 2.553 ns out2\[3\] 7 REG LC_X13_Y27_N8 4 " "Info: 7: + IC(0.000 ns) + CELL(0.497 ns) = 2.553 ns; Loc. = LC_X13_Y27_N8; Fanout = 4; REG Node = 'out2\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.497 ns" { out2[2]~47COUT1_51 out2[3] } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.507 ns ( 59.03 % ) " "Info: Total cell delay = 1.507 ns ( 59.03 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.046 ns ( 40.97 % ) " "Info: Total interconnect delay = 1.046 ns ( 40.97 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.553 ns" { out2[3] Equal1~28 process0~1 out2[0]~45COUT1_50 out2[1]~46COUT1 out2[2]~47COUT1_51 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.553 ns" { out2[3] Equal1~28 process0~1 out2[0]~45COUT1_50 out2[1]~46COUT1 out2[2]~47COUT1_51 out2[3] } { 0.000ns 0.410ns 0.330ns 0.306ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.366ns 0.183ns 0.341ns 0.060ns 0.060ns 0.497ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.930 ns + Shortest register " "Info: + Shortest clock path from clock \"clk1\" to destination register is 2.930 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk1 1 CLK PIN_M20 9 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'clk1'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.560 ns) + CELL(0.542 ns) 2.930 ns out2\[3\] 2 REG LC_X13_Y27_N8 4 " "Info: 2: + IC(1.560 ns) + CELL(0.542 ns) = 2.930 ns; Loc. = LC_X13_Y27_N8; Fanout = 4; REG Node = 'out2\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.102 ns" { clk1 out2[3] } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.76 % ) " "Info: Total cell delay = 1.370 ns ( 46.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.560 ns ( 53.24 % ) " "Info: Total interconnect delay = 1.560 ns ( 53.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.930 ns" { clk1 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.930 ns" { clk1 clk1~out0 out2[3] } { 0.000ns 0.000ns 1.560ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.930 ns - Longest register " "Info: - Longest clock path from clock \"clk1\" to source register is 2.930 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk1 1 CLK PIN_M20 9 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'clk1'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.560 ns) + CELL(0.542 ns) 2.930 ns out2\[3\] 2 REG LC_X13_Y27_N8 4 " "Info: 2: + IC(1.560 ns) + CELL(0.542 ns) = 2.930 ns; Loc. = LC_X13_Y27_N8; Fanout = 4; REG Node = 'out2\[3\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.102 ns" { clk1 out2[3] } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.76 % ) " "Info: Total cell delay = 1.370 ns ( 46.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.560 ns ( 53.24 % ) " "Info: Total interconnect delay = 1.560 ns ( 53.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.930 ns" { clk1 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.930 ns" { clk1 clk1~out0 out2[3] } { 0.000ns 0.000ns 1.560ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.930 ns" { clk1 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.930 ns" { clk1 clk1~out0 out2[3] } { 0.000ns 0.000ns 1.560ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.930 ns" { clk1 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.930 ns" { clk1 clk1~out0 out2[3] } { 0.000ns 0.000ns 1.560ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.553 ns" { out2[3] Equal1~28 process0~1 out2[0]~45COUT1_50 out2[1]~46COUT1 out2[2]~47COUT1_51 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.553 ns" { out2[3] Equal1~28 process0~1 out2[0]~45COUT1_50 out2[1]~46COUT1 out2[2]~47COUT1_51 out2[3] } { 0.000ns 0.410ns 0.330ns 0.306ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.366ns 0.183ns 0.341ns 0.060ns 0.060ns 0.497ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.930 ns" { clk1 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.930 ns" { clk1 clk1~out0 out2[3] } { 0.000ns 0.000ns 1.560ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.930 ns" { clk1 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.930 ns" { clk1 clk1~out0 out2[3] } { 0.000ns 0.000ns 1.560ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "co~reg0 clr clk1 -0.029 ns register " "Info: tsu for register \"co~reg0\" (data pin = \"clr\", clock pin = \"clk1\") is -0.029 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.891 ns + Longest pin register " "Info: + Longest pin to register delay is 2.891 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clr 1 PIN PIN_M21 9 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 9; PIN Node = 'clr'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.943 ns) + CELL(0.223 ns) 2.891 ns co~reg0 2 REG LC_X14_Y27_N2 2 " "Info: 2: + IC(1.943 ns) + CELL(0.223 ns) = 2.891 ns; Loc. = LC_X14_Y27_N2; Fanout = 2; REG Node = 'co~reg0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.166 ns" { clr co~reg0 } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.948 ns ( 32.79 % ) " "Info: Total cell delay = 0.948 ns ( 32.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.943 ns ( 67.21 % ) " "Info: Total interconnect delay = 1.943 ns ( 67.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.891 ns" { clr co~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.891 ns" { clr clr~out0 co~reg0 } { 0.000ns 0.000ns 1.943ns } { 0.000ns 0.725ns 0.223ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.930 ns - Shortest register " "Info: - Shortest clock path from clock \"clk1\" to destination register is 2.930 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk1 1 CLK PIN_M20 9 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'clk1'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.560 ns) + CELL(0.542 ns) 2.930 ns co~reg0 2 REG LC_X14_Y27_N2 2 " "Info: 2: + IC(1.560 ns) + CELL(0.542 ns) = 2.930 ns; Loc. = LC_X14_Y27_N2; Fanout = 2; REG Node = 'co~reg0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.102 ns" { clk1 co~reg0 } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.76 % ) " "Info: Total cell delay = 1.370 ns ( 46.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.560 ns ( 53.24 % ) " "Info: Total interconnect delay = 1.560 ns ( 53.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.930 ns" { clk1 co~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.930 ns" { clk1 clk1~out0 co~reg0 } { 0.000ns 0.000ns 1.560ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.891 ns" { clr co~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.891 ns" { clr clr~out0 co~reg0 } { 0.000ns 0.000ns 1.943ns } { 0.000ns 0.725ns 0.223ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.930 ns" { clk1 co~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.930 ns" { clk1 clk1~out0 co~reg0 } { 0.000ns 0.000ns 1.560ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk1 co co~reg0 6.977 ns register " "Info: tco from clock \"clk1\" to destination pin \"co\" through register \"co~reg0\" is 6.977 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.930 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to source register is 2.930 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk1 1 CLK PIN_M20 9 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'clk1'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.560 ns) + CELL(0.542 ns) 2.930 ns co~reg0 2 REG LC_X14_Y27_N2 2 " "Info: 2: + IC(1.560 ns) + CELL(0.542 ns) = 2.930 ns; Loc. = LC_X14_Y27_N2; Fanout = 2; REG Node = 'co~reg0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.102 ns" { clk1 co~reg0 } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.76 % ) " "Info: Total cell delay = 1.370 ns ( 46.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.560 ns ( 53.24 % ) " "Info: Total interconnect delay = 1.560 ns ( 53.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.930 ns" { clk1 co~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.930 ns" { clk1 clk1~out0 co~reg0 } { 0.000ns 0.000ns 1.560ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" { } { { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.891 ns + Longest register pin " "Info: + Longest register to pin delay is 3.891 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns co~reg0 1 REG LC_X14_Y27_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y27_N2; Fanout = 2; REG Node = 'co~reg0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { co~reg0 } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.487 ns) + CELL(2.404 ns) 3.891 ns co 2 PIN PIN_D15 0 " "Info: 2: + IC(1.487 ns) + CELL(2.404 ns) = 3.891 ns; Loc. = PIN_D15; Fanout = 0; PIN Node = 'co'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.891 ns" { co~reg0 co } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 61.78 % ) " "Info: Total cell delay = 2.404 ns ( 61.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.487 ns ( 38.22 % ) " "Info: Total interconnect delay = 1.487 ns ( 38.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.891 ns" { co~reg0 co } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.891 ns" { co~reg0 co } { 0.000ns 1.487ns } { 0.000ns 2.404ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.930 ns" { clk1 co~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.930 ns" { clk1 clk1~out0 co~reg0 } { 0.000ns 0.000ns 1.560ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.891 ns" { co~reg0 co } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.891 ns" { co~reg0 co } { 0.000ns 1.487ns } { 0.000ns 2.404ns } } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "co~reg0 clr clk1 0.139 ns register " "Info: th for register \"co~reg0\" (data pin = \"clr\", clock pin = \"clk1\") is 0.139 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 2.930 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to destination register is 2.930 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk1 1 CLK PIN_M20 9 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 9; CLK Node = 'clk1'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.560 ns) + CELL(0.542 ns) 2.930 ns co~reg0 2 REG LC_X14_Y27_N2 2 " "Info: 2: + IC(1.560 ns) + CELL(0.542 ns) = 2.930 ns; Loc. = LC_X14_Y27_N2; Fanout = 2; REG Node = 'co~reg0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.102 ns" { clk1 co~reg0 } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 46.76 % ) " "Info: Total cell delay = 1.370 ns ( 46.76 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.560 ns ( 53.24 % ) " "Info: Total interconnect delay = 1.560 ns ( 53.24 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.930 ns" { clk1 co~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.930 ns" { clk1 clk1~out0 co~reg0 } { 0.000ns 0.000ns 1.560ns } { 0.000ns 0.828ns 0.542ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.891 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.891 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clr 1 PIN PIN_M21 9 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 9; PIN Node = 'clr'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.943 ns) + CELL(0.223 ns) 2.891 ns co~reg0 2 REG LC_X14_Y27_N2 2 " "Info: 2: + IC(1.943 ns) + CELL(0.223 ns) = 2.891 ns; Loc. = LC_X14_Y27_N2; Fanout = 2; REG Node = 'co~reg0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.166 ns" { clr co~reg0 } "NODE_NAME" } } { "cdu60s.vhd" "" { Text "E:/多功能数字钟的设计/cdu60s/cdu60s.vhd" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.948 ns ( 32.79 % ) " "Info: Total cell delay = 0.948 ns ( 32.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.943 ns ( 67.21 % ) " "Info: Total interconnect delay = 1.943 ns ( 67.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.891 ns" { clr co~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.891 ns" { clr clr~out0 co~reg0 } { 0.000ns 0.000ns 1.943ns } { 0.000ns 0.725ns 0.223ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.930 ns" { clk1 co~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.930 ns" { clk1 clk1~out0 co~reg0 } { 0.000ns 0.000ns 1.560ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.891 ns" { clr co~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.891 ns" { clr clr~out0 co~reg0 } { 0.000ns 0.000ns 1.943ns } { 0.000ns 0.725ns 0.223ns } } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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