cdu60.map.qmsg

是一些很好的FPGA设计实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 10 22:41:54 2007 " "Info: Processing started: Wed Oct 10 22:41:54 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off cdu60 -c cdu60 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cdu60 -c cdu60" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cdu60.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cdu60.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cdu60-aa " "Info: Found design unit 1: cdu60-aa" {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 20 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 cdu60 " "Info: Found entity 1: cdu60" {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "cdu60 " "Info: Elaborating entity \"cdu60\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "out4 cdu60.vhd(22) " "Warning (10541): VHDL Signal Declaration warning at cdu60.vhd(22): used implicit default value for signal \"out4\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 22 0 0 } }  } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "out1 cdu60.vhd(45) " "Warning (10492): VHDL Process Statement warning at cdu60.vhd(45): signal \"out1\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 45 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "out2 cdu60.vhd(46) " "Warning (10492): VHDL Process Statement warning at cdu60.vhd(46): signal \"out2\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 46 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "out4 cdu60.vhd(47) " "Warning (10492): VHDL Process Statement warning at cdu60.vhd(47): signal \"out4\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 47 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "out3 cdu60.vhd(47) " "Warning (10492): VHDL Process Statement warning at cdu60.vhd(47): signal \"out3\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 47 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "m\[4\] GND " "Warning: Pin \"m\[4\]\" stuck at GND" {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 14 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m\[5\] GND " "Warning: Pin \"m\[5\]\" stuck at GND" {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 14 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m\[6\] GND " "Warning: Pin \"m\[6\]\" stuck at GND" {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 14 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m\[7\] GND " "Warning: Pin \"m\[7\]\" stuck at GND" {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 14 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "30 " "Info: Implemented 30 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "18 " "Info: Implemented 18 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 10 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 10 22:41:56 2007 " "Info: Processing ended: Wed Oct 10 22:41:56 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}