cdu60.tan.qmsg

是一些很好的FPGA设计实例

{ "Info" "ITDB_FULL_TPD_RESULT" "ss co 7.933 ns Longest " "Info: Longest tpd from source pin \"ss\" to destination pin \"co\" is 7.933 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns ss 1 CLK PIN_L22 2 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L22; Fanout = 2; CLK Node = 'ss'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ss } "NODE_NAME" } } { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.455 ns) + CELL(0.183 ns) 4.363 ns co~12 2 COMB LC_X1_Y19_N4 1 " "Info: 2: + IC(3.455 ns) + CELL(0.183 ns) = 4.363 ns; Loc. = LC_X1_Y19_N4; Fanout = 1; COMB Node = 'co~12'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.638 ns" { ss co~12 } "NODE_NAME" } } { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.194 ns) + CELL(2.376 ns) 7.933 ns co 3 PIN PIN_K21 0 " "Info: 3: + IC(1.194 ns) + CELL(2.376 ns) = 7.933 ns; Loc. = PIN_K21; Fanout = 0; PIN Node = 'co'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.570 ns" { co~12 co } "NODE_NAME" } } { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.284 ns ( 41.40 % ) " "Info: Total cell delay = 3.284 ns ( 41.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.649 ns ( 58.60 % ) " "Info: Total interconnect delay = 4.649 ns ( 58.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.933 ns" { ss co~12 co } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.933 ns" { ss ss~out0 co~12 co } { 0.000ns 0.000ns 3.455ns 1.194ns } { 0.000ns 0.725ns 0.183ns 2.376ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 10 22:42:18 2007 " "Info: Processing ended: Wed Oct 10 22:42:18 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}