cdu60.tan.qmsg

是一些很好的FPGA设计实例

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "ss " "Info: Assuming node \"ss\" is an undefined clock" {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 11 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "ss" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 11 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk2 " "Info: Assuming node \"clk2\" is an undefined clock" {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 11 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk2" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "clk~7 " "Info: Detected gated clock \"clk~7\" as buffer" {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 23 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk~7" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "ss register out1\[1\] register out2\[3\] 351.0 MHz 2.849 ns Internal " "Info: Clock \"ss\" has Internal fmax of 351.0 MHz between source register \"out1\[1\]\" and destination register \"out2\[3\]\" (period= 2.849 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.683 ns + Longest register register " "Info: + Longest register to register delay is 2.683 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns out1\[1\] 1 REG LC_X35_Y29_N9 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y29_N9; Fanout = 4; REG Node = 'out1\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { out1[1] } "NODE_NAME" } } { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.393 ns) + CELL(0.280 ns) 0.673 ns process0~51 2 COMB LC_X35_Y29_N5 3 " "Info: 2: + IC(0.393 ns) + CELL(0.280 ns) = 0.673 ns; Loc. = LC_X35_Y29_N5; Fanout = 3; COMB Node = 'process0~51'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.673 ns" { out1[1] process0~51 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.344 ns) + CELL(0.183 ns) 1.200 ns process0~1 3 COMB LC_X35_Y29_N8 6 " "Info: 3: + IC(0.344 ns) + CELL(0.183 ns) = 1.200 ns; Loc. = LC_X35_Y29_N8; Fanout = 6; COMB Node = 'process0~1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.527 ns" { process0~51 process0~1 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.525 ns) + CELL(0.341 ns) 2.066 ns out2\[0\]~45COUT1_50 4 COMB LC_X35_Y29_N1 2 " "Info: 4: + IC(0.525 ns) + CELL(0.341 ns) = 2.066 ns; Loc. = LC_X35_Y29_N1; Fanout = 2; COMB Node = 'out2\[0\]~45COUT1_50'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.866 ns" { process0~1 out2[0]~45COUT1_50 } "NODE_NAME" } } { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 2.126 ns out2\[1\]~46COUT1 5 COMB LC_X35_Y29_N2 2 " "Info: 5: + IC(0.000 ns) + CELL(0.060 ns) = 2.126 ns; Loc. = LC_X35_Y29_N2; Fanout = 2; COMB Node = 'out2\[1\]~46COUT1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.060 ns" { out2[0]~45COUT1_50 out2[1]~46COUT1 } "NODE_NAME" } } { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.060 ns) 2.186 ns out2\[2\]~47COUT1_51 6 COMB LC_X35_Y29_N3 1 " "Info: 6: + IC(0.000 ns) + CELL(0.060 ns) = 2.186 ns; Loc. = LC_X35_Y29_N3; Fanout = 1; COMB Node = 'out2\[2\]~47COUT1_51'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.060 ns" { out2[1]~46COUT1 out2[2]~47COUT1_51 } "NODE_NAME" } } { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.497 ns) 2.683 ns out2\[3\] 7 REG LC_X35_Y29_N4 5 " "Info: 7: + IC(0.000 ns) + CELL(0.497 ns) = 2.683 ns; Loc. = LC_X35_Y29_N4; Fanout = 5; REG Node = 'out2\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.497 ns" { out2[2]~47COUT1_51 out2[3] } "NODE_NAME" } } { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.421 ns ( 52.96 % ) " "Info: Total cell delay = 1.421 ns ( 52.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.262 ns ( 47.04 % ) " "Info: Total interconnect delay = 1.262 ns ( 47.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.683 ns" { out1[1] process0~51 process0~1 out2[0]~45COUT1_50 out2[1]~46COUT1 out2[2]~47COUT1_51 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.683 ns" { out1[1] process0~51 process0~1 out2[0]~45COUT1_50 out2[1]~46COUT1 out2[2]~47COUT1_51 out2[3] } { 0.000ns 0.393ns 0.344ns 0.525ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.280ns 0.183ns 0.341ns 0.060ns 0.060ns 0.497ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ss destination 5.033 ns + Shortest register " "Info: + Shortest clock path from clock \"ss\" to destination register is 5.033 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns ss 1 CLK PIN_L22 2 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L22; Fanout = 2; CLK Node = 'ss'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ss } "NODE_NAME" } } { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.598 ns) + CELL(0.075 ns) 1.398 ns clk~7 2 COMB LC_X1_Y19_N2 9 " "Info: 2: + IC(0.598 ns) + CELL(0.075 ns) = 1.398 ns; Loc. = LC_X1_Y19_N2; Fanout = 9; COMB Node = 'clk~7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.673 ns" { ss clk~7 } "NODE_NAME" } } { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.093 ns) + CELL(0.542 ns) 5.033 ns out2\[3\] 3 REG LC_X35_Y29_N4 5 " "Info: 3: + IC(3.093 ns) + CELL(0.542 ns) = 5.033 ns; Loc. = LC_X35_Y29_N4; Fanout = 5; REG Node = 'out2\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.635 ns" { clk~7 out2[3] } "NODE_NAME" } } { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.342 ns ( 26.66 % ) " "Info: Total cell delay = 1.342 ns ( 26.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.691 ns ( 73.34 % ) " "Info: Total interconnect delay = 3.691 ns ( 73.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.033 ns" { ss clk~7 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.033 ns" { ss ss~out0 clk~7 out2[3] } { 0.000ns 0.000ns 0.598ns 3.093ns } { 0.000ns 0.725ns 0.075ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ss source 5.033 ns - Longest register " "Info: - Longest clock path from clock \"ss\" to source register is 5.033 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns ss 1 CLK PIN_L22 2 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L22; Fanout = 2; CLK Node = 'ss'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ss } "NODE_NAME" } } { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.598 ns) + CELL(0.075 ns) 1.398 ns clk~7 2 COMB LC_X1_Y19_N2 9 " "Info: 2: + IC(0.598 ns) + CELL(0.075 ns) = 1.398 ns; Loc. = LC_X1_Y19_N2; Fanout = 9; COMB Node = 'clk~7'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.673 ns" { ss clk~7 } "NODE_NAME" } } { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.093 ns) + CELL(0.542 ns) 5.033 ns out1\[1\] 3 REG LC_X35_Y29_N9 4 " "Info: 3: + IC(3.093 ns) + CELL(0.542 ns) = 5.033 ns; Loc. = LC_X35_Y29_N9; Fanout = 4; REG Node = 'out1\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.635 ns" { clk~7 out1[1] } "NODE_NAME" } } { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.342 ns ( 26.66 % ) " "Info: Total cell delay = 1.342 ns ( 26.66 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.691 ns ( 73.34 % ) " "Info: Total interconnect delay = 3.691 ns ( 73.34 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.033 ns" { ss clk~7 out1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.033 ns" { ss ss~out0 clk~7 out1[1] } { 0.000ns 0.000ns 0.598ns 3.093ns } { 0.000ns 0.725ns 0.075ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.033 ns" { ss clk~7 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.033 ns" { ss ss~out0 clk~7 out2[3] } { 0.000ns 0.000ns 0.598ns 3.093ns } { 0.000ns 0.725ns 0.075ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.033 ns" { ss clk~7 out1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.033 ns" { ss ss~out0 clk~7 out1[1] } { 0.000ns 0.000ns 0.598ns 3.093ns } { 0.000ns 0.725ns 0.075ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "cdu60.vhd" "" { Text "E:/多功能数字钟的设计/cdu60/cdu60.vhd" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.683 ns" { out1[1] process0~51 process0~1 out2[0]~45COUT1_50 out2[1]~46COUT1 out2[2]~47COUT1_51 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.683 ns" { out1[1] process0~51 process0~1 out2[0]~45COUT1_50 out2[1]~46COUT1 out2[2]~47COUT1_51 out2[3] } { 0.000ns 0.393ns 0.344ns 0.525ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.280ns 0.183ns 0.341ns 0.060ns 0.060ns 0.497ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.033 ns" { ss clk~7 out2[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.033 ns" { ss ss~out0 clk~7 out2[3] } { 0.000ns 0.000ns 0.598ns 3.093ns } { 0.000ns 0.725ns 0.075ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.033 ns" { ss clk~7 out1[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.033 ns" { ss ss~out0 clk~7 out1[1] } { 0.000ns 0.000ns 0.598ns 3.093ns } { 0.000ns 0.725ns 0.075ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}