pwm_hw.tcl

pwm模块pwm模块pwm模块pwm模块pwm模块

# TCL File Generated by Component Editor 8.0
# Fri May 08 15:03:57 CST 2009
# DO NOT MODIFY


# +-----------------------------------
# | 
# | pwm "pwm" v1.0
# | null 2009.05.08.15:03:57
# | 
# | 
# | D:/bysj/PWM2/13-PWM信号产生/pwm.vhd
# | 
# |    ./pwm.vhd syn, sim
# | 
# +-----------------------------------


# +-----------------------------------
# | module pwm
# | 
set_module_property NAME pwm
set_module_property VERSION 1.0
set_module_property GROUP ""
set_module_property DISPLAY_NAME pwm
set_module_property LIBRARIES {ieee.std_logic_1164.all ieee.std_logic_arith.all ieee.std_logic_unsigned.all std.standard.all}
set_module_property TOP_LEVEL_HDL_FILE pwm.vhd
set_module_property TOP_LEVEL_HDL_MODULE pwm
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE false
set_module_property SIMULATION_MODEL_IN_VERILOG false
set_module_property SIMULATION_MODEL_IN_VHDL false
set_module_property SIMULATION_MODEL_HAS_TULIPS false
set_module_property SIMULATION_MODEL_IS_OBFUSCATED false
# | 
# +-----------------------------------

# +-----------------------------------
# | files
# | 
add_file pwm.vhd {SYNTHESIS SIMULATION}
# | 
# +-----------------------------------

# +-----------------------------------
# | parameters
# | 
add_parameter pulse_width int 2
set_parameter_property pulse_width DISPLAY_NAME pulse_width
set_parameter_property pulse_width UNITS None
set_parameter_property pulse_width AFFECTS_PORT_WIDTHS true
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point clock_reset
# | 
add_interface clock_reset clock end
set_interface_property clock_reset ptfSchematicName ""

add_interface_port clock_reset clock_out export Output 1
add_interface_port clock_reset clock reset_n Input 1
add_interface_port clock_reset reset reset Input 1
# | 
# +-----------------------------------

# +-----------------------------------
# | connection point avalon_slave_0
# | 
add_interface avalon_slave_0 avalon end
set_interface_property avalon_slave_0 holdTime 0
set_interface_property avalon_slave_0 linewrapBursts false
set_interface_property avalon_slave_0 minimumUninterruptedRunLength 1
set_interface_property avalon_slave_0 bridgesToMaster ""
set_interface_property avalon_slave_0 isMemoryDevice false
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
set_interface_property avalon_slave_0 timingUnits Cycles
set_interface_property avalon_slave_0 setupTime 0
set_interface_property avalon_slave_0 writeWaitTime 0
set_interface_property avalon_slave_0 isNonVolatileStorage false
set_interface_property avalon_slave_0 addressAlignment DYNAMIC
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
set_interface_property avalon_slave_0 readWaitTime 1
set_interface_property avalon_slave_0 readLatency 0
set_interface_property avalon_slave_0 printableDevice false

set_interface_property avalon_slave_0 ASSOCIATED_CLOCK clock_reset

add_interface_port avalon_slave_0 clock_m beginbursttransfer_n Input 1
# | 
# +-----------------------------------