unnamed.sopc

pwm模块pwm模块pwm模块pwm模块pwm模块

<?xml version="1.0" encoding="UTF-8"?><system name="unnamed">
    <parameter name="bonusData">bonusData 
{
   element clk
   {
      datum _sortIndex
      {
         value = "0";
         type = "int";
      }
   }
}
</parameter>
    <parameter name="deviceFamily" value="CYCLONEII" />
    <parameter name="generateLegacySim" value="false" />
    <parameter name="hardcopyCompatible" value="false" />
    <parameter name="hdlLanguage" value="VHDL" />
    <parameter name="projectName" value="pwm_gen.quartus" />
    <parameter name="systemHash" value="-1502317918" />
    <parameter name="timeStamp" value="1239607564125" />
    <module name="clk" kind="clock_source" version="8.0" enabled="1">
        <parameter name="clockFrequency" value="50000000" />
        <parameter name="clockFrequencyKnown" value="true" />
    </module>
</system>