pwm_gen.map.rpt

pwm模块pwm模块pwm模块pwm模块pwm模块

Analysis & Synthesis report for pwm_gen
Mon Apr 13 15:22:10 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Registers Removed During Synthesis
  8. Source assignments for pwm:inst4|lpm_counter:delay_counter_rtl_0
  9. Source assignments for pwm_counter:inst|lpm_add_sub:Add0|addcore:adder[1]
 10. Source assignments for pwm_counter:inst|lpm_add_sub:Add0|addcore:adder[0]
 11. Source assignments for counter:inst3|lpm_add_sub:Add0|addcore:adder[1]
 12. Source assignments for counter:inst3|lpm_add_sub:Add0|addcore:adder[0]
 13. Source assignments for pwm_counter:inst|lpm_add_sub:Add2|addcore:adder[2]
 14. Source assignments for pwm_counter:inst|lpm_add_sub:Add2|addcore:adder[1]
 15. Source assignments for pwm_counter:inst|lpm_add_sub:Add2|addcore:adder[0]
 16. Source assignments for pwm_counter:inst|lpm_add_sub:Add1|addcore:adder
 17. Source assignments for pwm_counter:inst|lpm_add_sub:Add1|addcore:adder|addcore:adder[0]
 18. Parameter Settings for User Entity Instance: pwm:inst4
 19. Parameter Settings for User Entity Instance: pwm_counter:inst
 20. Parameter Settings for User Entity Instance: counter:inst3
 21. Parameter Settings for Inferred Entity Instance: pwm:inst4|lpm_counter:delay_counter_rtl_0
 22. Parameter Settings for Inferred Entity Instance: pwm_counter:inst|lpm_add_sub:Add0
 23. Parameter Settings for Inferred Entity Instance: counter:inst3|lpm_add_sub:Add0
 24. Parameter Settings for Inferred Entity Instance: pwm_counter:inst|lpm_add_sub:Add2
 25. Parameter Settings for Inferred Entity Instance: pwm_counter:inst|lpm_add_sub:Add1
 26. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Apr 13 15:22:10 2009    ;
; Quartus II Version          ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name               ; pwm_gen                                  ;
; Top-level Entity Name       ; pwm_gen                                  ;
; Family                      ; MAX3000A                                 ;
; Total macrocells            ; 116                                      ;
; Total pins                  ; 5                                        ;
+-----------------------------+------------------------------------------+


+-------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                   ;
+--------------------------------------------------------------+------------------+---------------+
; Option                                                       ; Setting          ; Default Value ;
+--------------------------------------------------------------+------------------+---------------+
; Device                                                       ; EPM3128ATC100-10 ;               ;
; Top-level entity name                                        ; pwm_gen          ; pwm_gen       ;
; Family name                                                  ; MAX3000A         ; Stratix       ;
; Use smart compilation                                        ; Off              ; Off           ;
; Create Debugging Nodes for IP Cores                          ; Off              ; Off           ;
; Preserve fewer node names                                    ; On               ; On            ;
; Disable OpenCore Plus hardware evaluation                    ; Off              ; Off           ;
; Verilog Version                                              ; Verilog_2001     ; Verilog_2001  ;
; VHDL Version                                                 ; VHDL93           ; VHDL93        ;
; State Machine Processing                                     ; Auto             ; Auto          ;
; Safe State Machine                                           ; Off              ; Off           ;
; Extract Verilog State Machines                               ; On               ; On            ;
; Extract VHDL State Machines                                  ; On               ; On            ;
; Ignore Verilog initial constructs                            ; Off              ; Off           ;
; Iteration limit for constant Verilog loops                   ; 5000             ; 5000          ;
; Iteration limit for non-constant Verilog loops               ; 250              ; 250           ;
; Add Pass-Through Logic to Inferred RAMs                      ; On               ; On            ;
; Parallel Synthesis                                           ; Off              ; Off           ;
; NOT Gate Push-Back                                           ; On               ; On            ;
; Power-Up Don't Care                                          ; On               ; On            ;
; Remove Duplicate Registers                                   ; On               ; On            ;
; Ignore CARRY Buffers                                         ; Off              ; Off           ;
; Ignore CASCADE Buffers                                       ; Off              ; Off           ;
; Ignore GLOBAL Buffers                                        ; Off              ; Off           ;
; Ignore ROW GLOBAL Buffers                                    ; Off              ; Off           ;
; Ignore LCELL Buffers                                         ; Auto             ; Auto          ;
; Ignore SOFT Buffers                                          ; Off              ; Off           ;
; Limit AHDL Integers to 32 Bits                               ; Off              ; Off           ;
; Optimization Technique                                       ; Speed            ; Speed         ;
; Allow XOR Gate Usage                                         ; On               ; On            ;
; Auto Logic Cell Insertion                                    ; On               ; On            ;
; Parallel Expander Chain Length                               ; 4                ; 4             ;
; Auto Parallel Expanders                                      ; On               ; On            ;
; Auto Open-Drain Pins                                         ; On               ; On            ;
; Auto Resource Sharing                                        ; Off              ; Off           ;
; Maximum Fan-in Per Macrocell                                 ; 100              ; 100           ;
; Ignore translate_off and synthesis_off directives            ; Off              ; Off           ;
; Show Parameter Settings Tables in Synthesis Report           ; On               ; On            ;
; HDL message level                                            ; Level2           ; Level2        ;
; Suppress Register Optimization Related Messages              ; Off              ; Off           ;
; Number of Removed Registers Reported in Synthesis Report     ; 100              ; 100           ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100              ; 100           ;
; Block Design Naming                                          ; Auto             ; Auto          ;
; Synthesis Effort                                             ; Auto             ; Auto          ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On               ; On            ;
+--------------------------------------------------------------+------------------+---------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                         ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                         ;
+----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------------+
; counter.vhd                      ; yes             ; User VHDL File                     ; D:/bysj/PWM2/13-PWM信号产生/counter.vhd                              ;
; pwm.vhd                          ; yes             ; User VHDL File                     ; D:/bysj/PWM2/13-PWM信号产生/pwm.vhd                                  ;
; pwm_gen.bdf                      ; yes             ; User Block Diagram/Schematic File  ; D:/bysj/PWM2/13-PWM信号产生/pwm_gen.bdf                              ;
; serialport_tx.vhd                ; yes             ; User VHDL File                     ; D:/bysj/PWM2/13-PWM信号产生/serialport_tx.vhd                        ;
; pwm_counter.vhd                  ; yes             ; User VHDL File                     ; D:/bysj/PWM2/13-PWM信号产生/pwm_counter.vhd                          ;
; lpm_counter.tdf                  ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_constant.inc                 ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/lpm_constant.inc        ;
; lpm_decode.inc                   ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc          ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; Megafunction                       ; d:/altera/80/quartus/libraries/megafunctions/alt_counter_stratix.inc ;