medical.tan.rpt

利用FPGA来实现一个简单的医疗呼叫系统

; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Apr 17 20:59:07 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off medical -c medical --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "clk2" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 500.0 MHz between source register "cntt[5]~reg0" and destination register "cntt[3]~reg0"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.307 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y18_N29; Fanout = 4; REG Node = 'cntt[5]~reg0'
            Info: 2: + IC(0.412 ns) + CELL(0.272 ns) = 0.684 ns; Loc. = LCCOMB_X1_Y18_N24; Fanout = 2; COMB Node = 'Equal1~41'
            Info: 3: + IC(0.240 ns) + CELL(0.228 ns) = 1.152 ns; Loc. = LCCOMB_X1_Y18_N30; Fanout = 1; COMB Node = 'cntt~108'
            Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 1.307 ns; Loc. = LCFF_X1_Y18_N31; Fanout = 5; REG Node = 'cntt[3]~reg0'
            Info: Total cell delay = 0.655 ns ( 50.11 % )
            Info: Total interconnect delay = 0.652 ns ( 49.89 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.458 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 40; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.643 ns) + CELL(0.618 ns) = 2.458 ns; Loc. = LCFF_X1_Y18_N31; Fanout = 5; REG Node = 'cntt[3]~reg0'
                Info: Total cell delay = 1.472 ns ( 59.89 % )
                Info: Total interconnect delay = 0.986 ns ( 40.11 % )
            Info: - Longest clock path from clock "clk" to source register is 2.458 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 40; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.643 ns) + CELL(0.618 ns) = 2.458 ns; Loc. = LCFF_X1_Y18_N29; Fanout = 4; REG Node = 'cntt[5]~reg0'
                Info: Total cell delay = 1.472 ns ( 59.89 % )
                Info: Total interconnect delay = 0.986 ns ( 40.11 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: Clock "clk2" Internal fmax is restricted to 500.0 MHz between source register "cnt[3]~reg0" and destination register "cnt[2]~reg0"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.306 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X38_Y19_N3; Fanout = 15; REG Node = 'cnt[3]~reg0'
            Info: 2: + IC(0.443 ns) + CELL(0.346 ns) = 0.789 ns; Loc. = LCCOMB_X38_Y19_N8; Fanout = 6; COMB Node = 'Add0~94'
            Info: 3: + IC(0.309 ns) + CELL(0.053 ns) = 1.151 ns; Loc. = LCCOMB_X38_Y19_N12; Fanout = 1; COMB Node = 'cnt[2]~234'
            Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 1.306 ns; Loc. = LCFF_X38_Y19_N13; Fanout = 19; REG Node = 'cnt[2]~reg0'
            Info: Total cell delay = 0.554 ns ( 42.42 % )
            Info: Total interconnect delay = 0.752 ns ( 57.58 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk2" to destination register is 2.495 ns
                Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'clk2'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 13; COMB Node = 'clk2~clkctrl'
                Info: 3: + IC(0.670 ns) + CELL(0.618 ns) = 2.495 ns; Loc. = LCFF_X38_Y19_N13; Fanout = 19; REG Node = 'cnt[2]~reg0'
                Info: Total cell delay = 1.482 ns ( 59.40 % )
                Info: Total interconnect delay = 1.013 ns ( 40.60 % )
            Info: - Longest clock path from clock "clk2" to source register is 2.495 ns
                Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'clk2'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 13; COMB Node = 'clk2~clkctrl'
                Info: 3: + IC(0.670 ns) + CELL(0.618 ns) = 2.495 ns; Loc. = LCFF_X38_Y19_N3; Fanout = 15; REG Node = 'cnt[3]~reg0'
                Info: Total cell delay = 1.482 ns ( 59.40 % )
                Info: Total interconnect delay = 1.013 ns ( 40.60 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "fenji:fenji_u5|out" (data pin = "err[5]", clock pin = "clk") is 3.144 ns
    Info: + Longest pin to register delay is 5.541 ns
        Info: 1: + IC(0.000 ns) + CELL(0.817 ns) = 0.817 ns; Loc. = PIN_U9; Fanout = 1; PIN Node = 'err[5]'
        Info: 2: + IC(4.415 ns) + CELL(0.309 ns) = 5.541 ns; Loc. = LCFF_X38_Y16_N11; Fanout = 2; REG Node = 'fenji:fenji_u5|out'
        Info: Total cell delay = 1.126 ns ( 20.32 % )
        Info: Total interconnect delay = 4.415 ns ( 79.68 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.487 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 40; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.672 ns) + CELL(0.618 ns) = 2.487 ns; Loc. = LCFF_X38_Y16_N11; Fanout = 2; REG Node = 'fenji:fenji_u5|out'
        Info: Total cell delay = 1.472 ns ( 59.19 % )
        Info: Total interconnect delay = 1.015 ns ( 40.81 % )
Info: tco from clock "clk2" to destination pin "cnt[3]" through register "cnt[3]~reg0" is 7.344 ns
    Info: + Longest clock path from clock "clk2" to source register is 2.495 ns
        Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'clk2'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 13; COMB Node = 'clk2~clkctrl'
        Info: 3: + IC(0.670 ns) + CELL(0.618 ns) = 2.495 ns; Loc. = LCFF_X38_Y19_N3; Fanout = 15; REG Node = 'cnt[3]~reg0'
        Info: Total cell delay = 1.482 ns ( 59.40 % )
        Info: Total interconnect delay = 1.013 ns ( 40.60 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 4.755 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X38_Y19_N3; Fanout = 15; REG Node = 'cnt[3]~reg0'
        Info: 2: + IC(2.783 ns) + CELL(1.972 ns) = 4.755 ns; Loc. = PIN_W5; Fanout = 0; PIN Node = 'cnt[3]'
        Info: Total cell delay = 1.972 ns ( 41.47 % )
        Info: Total interconnect delay = 2.783 ns ( 58.53 % )
Info: th for register "fenji:fenji_u0|out" (data pin = "err[0]", clock pin = "clk") is -1.831 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.480 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 40; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.665 ns) + CELL(0.618 ns) = 2.480 ns; Loc. = LCFF_X39_Y18_N17; Fanout = 2; REG Node = 'fenji:fenji_u0|out'
        Info: Total cell delay = 1.472 ns ( 59.35 % )
        Info: Total interconnect delay = 1.008 ns ( 40.65 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 4.460 ns
        Info: 1: + IC(0.000 ns) + CELL(0.810 ns) = 0.810 ns; Loc. = PIN_K3; Fanout = 1; PIN Node = 'err[0]'
        Info: 2: + IC(3.442 ns) + CELL(0.053 ns) = 4.305 ns; Loc. = LCCOMB_X39_Y18_N16; Fanout = 1; COMB Node = 'fenji:fenji_u0|out~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 4.460 ns; Loc. = LCFF_X39_Y18_N17; Fanout = 2; REG Node = 'fenji:fenji_u0|out'
        Info: Total cell delay = 1.018 ns ( 22.83 % )
        Info: Total interconnect delay = 3.442 ns ( 77.17 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 115 megabytes of memory during processing
    Info: Processing ended: Fri Apr 17 20:59:08 2009
    Info: Elapsed time: 00:00:01