latchinf.v

verilog 范例

// MAX+plus II Verilog Example
// Latch Inference
// Copyright (c) 1997 Altera Corporation

module latchinf(enable, data, q);

    input enable, data;
    output q;
    reg q;

    always @(enable or data)
	if (enable)
		q <= data;

endmodule