dft.txt

verilog语言实在点变换DFT源代码

`define   N      1024    //对N点数据作DFT
`define   L      180     
/*************************************************/
module dft( Clk,   //全局时钟24MHz
            Run_Stop,
            //ADC
            ADin,  //AD数据输入
            ADC_Clk, //AD时钟输出
            //CPU
            CPU_Addr,
            CPU_DB,            
            Sample_Time,   //采样时间输入
            //
            End_INT
            );      
   /*************************************************/
   input Clk;
   input Run_Stop;
   input [7:0] ADin;
   output ADC_Clk;
   reg ADC_Clk;
   input [8:0] CPU_Addr;
   output [31:0] CPU_DB;
   input [14:0] Sample_Time; 
   output End_INT;
   reg End_INT;
   /********************ADC_Clk*********************/
   reg [5:0] ADC_Clk_Count;
   always @(posedge Clk) /*****上升沿触发  
     begin
       if(ADC_Clk_Count<48)
          ADC_Clk_Count <= ADC_Clk_Count+1;
       else
          ADC_Clk_Count <=1;
     end
   always @(posedge Clk)//ADC Clk = 500KHz
     begin
       if(ADC_Clk_Count==1)
          ADC_Clk <= 1;
       else if(ADC_Clk_Count==25)
          ADC_Clk <= 0;
     end
   /********************ADin***********************/
   reg [7:0]  Dreg;
   always @(posedge ADC_Clk)   //数据调整，将ADC输入的数据转换成有符号数
     begin
       if(ADin>=8'h80)
         Dreg <= ADin & 8'h7f;
       else
         Dreg <= ADin | 8'h80;
     end
   /*****************Sample_Data******************/
   reg Sample_Flag;
   reg [9:0] Sample_Addr;
   reg [14:0] Sample_Count;
   reg Sample_WE;
   always @(posedge Clk)   //采样允许标志
     begin
       if(CPU_Addr==9'h1ff)
          Sample_Flag <= 1;
       else if(Sample_Addr==`N-1 && Sample_WE)
          Sample_Flag <= 0;
     end
     
   always @(posedge Clk)
     begin
       if(Sample_Count<Sample_Time)
         Sample_Count <= Sample_Count+1;
       else
         Sample_Count <= 1;
     end
   always @(posedge Clk)
     begin
       if(Sample_Count+1==Sample_Time && Sample_Flag)
         Sample_WE <= 1;
       else if(Sample_Count==1)
         Sample_WE <= 0;
     end
   always @(posedge Clk)
     begin
       if(CPU_Addr==9'h1ff)
          Sample_Addr <= 0;
       else if(Sample_Count==Sample_Time && Sample_Flag)
          Sample_Addr <= Sample_Addr+1;       
     end
  
//   RAM_DIN mram_din(Dreg,Sample_WE&Run_Stop,Sample_Addr,J,Clk,DFT_DB);
   RAM_DIN mram_din(Clk,Dreg,J,Sample_Addr,Sample_WE&Run_Stop,DFT_DB);   //Updata to 7.1 Version by Liu Zenglin
   /*****************DFT******************/
   reg DFT_Flag;
   wire [7:0] DFT_DB;
   wire [31:0] EX_DFT_DB = DFT_DB[7]?{24'hffffff,DFT_DB}:DFT_DB; //符号扩展
   always @(posedge Clk)
     begin
       if(Sample_Flag || I==`L)
         DFT_Flag <= 0;
       else if(Sample_Addr==`N-1)
         DFT_Flag <= 1;
     end   
   
   reg [7:0] I;
   reg [9:0] J;
   always @(posedge Clk)
     begin
       if(DFT_Flag)
         begin
           J <= J+1;
           if(J==`N-1)
              I <= I+1;
         end
       else
         begin
           I <= 0;
           J <= 0;
         end
     end
   wire [9:0] Sin_Addr = I*J; 
   wire [9:0] Cos_Addr = Sin_Addr+256;
   wire [7:0] Sin_DB,Cos_DB;   
//   ROM_SIN mrom_sin(Clk,Sin_Addr,Cos_Addr,Sin_DB,Cos_DB);   
   ROM_SIN mrom_sin(Sin_Addr,Cos_Addr,Clk,Sin_DB,Cos_DB);	
   wire [31:0] EX_Sin_DB = Sin_DB[7]?{24'hffffff,Sin_DB}:Sin_DB; //符号扩展
   wire [31:0] EX_Cos_DB = Cos_DB[7]?{24'hffffff,Cos_DB}:Cos_DB; //符号扩展

   reg DFT_WE;
   always @(posedge Clk)
     begin
       if(DFT_Flag && J==0)
          DFT_WE <= 1;
       else
          DFT_WE <= 0;
     end
     
   reg [31:0] Xr,Xi;
   wire III = (I==0 ||(I==1 && J==0))? 0:1;
   wire [31:0] Xr_Mul = III ? EX_DFT_DB*EX_Cos_DB:EX_DFT_DB;
   wire [31:0] Xi_Mul = III ? EX_DFT_DB*EX_Sin_DB:0;
   always @(posedge Clk)
     begin
       if(DFT_Flag)
          begin
            if(J==1)
              begin
                Xr <= Xr_Mul;
                Xi <= Xi_Mul;
              end
            else
              begin         
                Xr <= Xr+Xr_Mul;
                Xi <= Xi-Xi_Mul;
              end
          end
       else
          begin
            Xr <= 0;
            Xi <= 0;
          end
     end
   /************DFT Write Data & CPU Read Data***************/
   wire [31:0] Xr_Out,Xi_Out;
//   RAM_X mram_xr(Xr,DFT_WE,I-1,CPU_Addr,Clk,Xr_Out);
   RAM_X mram_xr(Clk,Xr,CPU_Addr,I-1,DFT_WE,Xr_Out);	
//   RAM_X mram_xi(Xi,DFT_WE,I-1,CPU_Addr,Clk,Xi_Out);
   RAM_X mram_xi(Clk,Xi,CPU_Addr,I-1,DFT_WE,Xi_Out);	
   assign CPU_DB = CPU_Addr[8]? Xi_Out:Xr_Out;
   
   /****************End Indicate*****************************/
   always @(posedge Clk)
     begin
       if(CPU_Addr==9'h1ff)
          End_INT <= 1;
       else if(DFT_Flag || I==`L)
          End_INT <= 0;
     end
   
endmodule