clk_div.tan.qmsg

VHDL语言描述

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk500K_1 " "Info: Detected ripple clock \"clk500K_1\" as buffer" {  } { { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 28 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk500K_1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk10K_1 " "Info: Detected ripple clock \"clk10K_1\" as buffer" {  } { { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 36 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk10K_1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk1M_1 " "Info: Detected ripple clock \"clk1M_1\" as buffer" {  } { { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 18 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1M_1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk50M register \\process4:cnt\[2\] register \\process4:cnt\[4\] 172.77 MHz 5.788 ns Internal " "Info: Clock \"clk50M\" has Internal fmax of 172.77 MHz between source register \"\\process4:cnt\[2\]\" and destination register \"\\process4:cnt\[4\]\" (period= 5.788 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.079 ns + Longest register register " "Info: + Longest register to register delay is 5.079 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns \\process4:cnt\[2\] 1 REG LC_X13_Y10_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y10_N0; Fanout = 4; REG Node = '\\process4:cnt\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { \process4:cnt[2] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.293 ns) + CELL(0.978 ns) 2.271 ns Add2~90 2 COMB LC_X14_Y10_N3 2 " "Info: 2: + IC(1.293 ns) + CELL(0.978 ns) = 2.271 ns; Loc. = LC_X14_Y10_N3; Fanout = 2; COMB Node = 'Add2~90'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { \process4:cnt[2] Add2~90 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.261 ns) 2.532 ns Add2~94 3 COMB LC_X14_Y10_N4 2 " "Info: 3: + IC(0.000 ns) + CELL(0.261 ns) = 2.532 ns; Loc. = LC_X14_Y10_N4; Fanout = 2; COMB Node = 'Add2~94'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.261 ns" { Add2~90 Add2~94 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 3.507 ns Add2~95 4 COMB LC_X14_Y10_N5 1 " "Info: 4: + IC(0.000 ns) + CELL(0.975 ns) = 3.507 ns; Loc. = LC_X14_Y10_N5; Fanout = 1; COMB Node = 'Add2~95'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.975 ns" { Add2~94 Add2~95 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.768 ns) + CELL(0.804 ns) 5.079 ns \\process4:cnt\[4\] 5 REG LC_X14_Y10_N9 7 " "Info: 5: + IC(0.768 ns) + CELL(0.804 ns) = 5.079 ns; Loc. = LC_X14_Y10_N9; Fanout = 7; REG Node = '\\process4:cnt\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { Add2~95 \process4:cnt[4] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.018 ns ( 59.42 % ) " "Info: Total cell delay = 3.018 ns ( 59.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.061 ns ( 40.58 % ) " "Info: Total interconnect delay = 2.061 ns ( 40.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.079 ns" { \process4:cnt[2] Add2~90 Add2~94 Add2~95 \process4:cnt[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.079 ns" { \process4:cnt[2] {} Add2~90 {} Add2~94 {} Add2~95 {} \process4:cnt[4] {} } { 0.000ns 1.293ns 0.000ns 0.000ns 0.768ns } { 0.000ns 0.978ns 0.261ns 0.975ns 0.804ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50M destination 16.071 ns + Shortest register " "Info: + Shortest clock path from clock \"clk50M\" to destination register is 16.071 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk50M 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk50M'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk50M } "NODE_NAME" } } { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clk1M_1 2 REG LC_X10_Y4_N2 3 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y4_N2; Fanout = 3; REG Node = 'clk1M_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk50M clk1M_1 } "NODE_NAME" } } { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.866 ns) + CELL(1.294 ns) 6.355 ns clk500K_1 3 REG LC_X10_Y4_N7 8 " "Info: 3: + IC(0.866 ns) + CELL(1.294 ns) = 6.355 ns; Loc. = LC_X10_Y4_N7; Fanout = 8; REG Node = 'clk500K_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.160 ns" { clk1M_1 clk500K_1 } "NODE_NAME" } } { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.453 ns) + CELL(1.294 ns) 12.102 ns clk10K_1 4 REG LC_X12_Y3_N2 9 " "Info: 4: + IC(4.453 ns) + CELL(1.294 ns) = 12.102 ns; Loc. = LC_X12_Y3_N2; Fanout = 9; REG Node = 'clk10K_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.747 ns" { clk500K_1 clk10K_1 } "NODE_NAME" } } { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.051 ns) + CELL(0.918 ns) 16.071 ns \\process4:cnt\[4\] 5 REG LC_X14_Y10_N9 7 " "Info: 5: + IC(3.051 ns) + CELL(0.918 ns) = 16.071 ns; Loc. = LC_X14_Y10_N9; Fanout = 7; REG Node = '\\process4:cnt\[4\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.969 ns" { clk10K_1 \process4:cnt[4] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.963 ns ( 37.10 % ) " "Info: Total cell delay = 5.963 ns ( 37.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.108 ns ( 62.90 % ) " "Info: Total interconnect delay = 10.108 ns ( 62.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.071 ns" { clk50M clk1M_1 clk500K_1 clk10K_1 \process4:cnt[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.071 ns" { clk50M {} clk50M~combout {} clk1M_1 {} clk500K_1 {} clk10K_1 {} \process4:cnt[4] {} } { 0.000ns 0.000ns 1.738ns 0.866ns 4.453ns 3.051ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50M source 16.071 ns - Longest register " "Info: - Longest clock path from clock \"clk50M\" to source register is 16.071 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk50M 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk50M'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk50M } "NODE_NAME" } } { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clk1M_1 2 REG LC_X10_Y4_N2 3 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y4_N2; Fanout = 3; REG Node = 'clk1M_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk50M clk1M_1 } "NODE_NAME" } } { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.866 ns) + CELL(1.294 ns) 6.355 ns clk500K_1 3 REG LC_X10_Y4_N7 8 " "Info: 3: + IC(0.866 ns) + CELL(1.294 ns) = 6.355 ns; Loc. = LC_X10_Y4_N7; Fanout = 8; REG Node = 'clk500K_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.160 ns" { clk1M_1 clk500K_1 } "NODE_NAME" } } { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.453 ns) + CELL(1.294 ns) 12.102 ns clk10K_1 4 REG LC_X12_Y3_N2 9 " "Info: 4: + IC(4.453 ns) + CELL(1.294 ns) = 12.102 ns; Loc. = LC_X12_Y3_N2; Fanout = 9; REG Node = 'clk10K_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.747 ns" { clk500K_1 clk10K_1 } "NODE_NAME" } } { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.051 ns) + CELL(0.918 ns) 16.071 ns \\process4:cnt\[2\] 5 REG LC_X13_Y10_N0 4 " "Info: 5: + IC(3.051 ns) + CELL(0.918 ns) = 16.071 ns; Loc. = LC_X13_Y10_N0; Fanout = 4; REG Node = '\\process4:cnt\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.969 ns" { clk10K_1 \process4:cnt[2] } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.963 ns ( 37.10 % ) " "Info: Total cell delay = 5.963 ns ( 37.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.108 ns ( 62.90 % ) " "Info: Total interconnect delay = 10.108 ns ( 62.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.071 ns" { clk50M clk1M_1 clk500K_1 clk10K_1 \process4:cnt[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.071 ns" { clk50M {} clk50M~combout {} clk1M_1 {} clk500K_1 {} clk10K_1 {} \process4:cnt[2] {} } { 0.000ns 0.000ns 1.738ns 0.866ns 4.453ns 3.051ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.071 ns" { clk50M clk1M_1 clk500K_1 clk10K_1 \process4:cnt[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.071 ns" { clk50M {} clk50M~combout {} clk1M_1 {} clk500K_1 {} clk10K_1 {} \process4:cnt[4] {} } { 0.000ns 0.000ns 1.738ns 0.866ns 4.453ns 3.051ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.071 ns" { clk50M clk1M_1 clk500K_1 clk10K_1 \process4:cnt[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.071 ns" { clk50M {} clk50M~combout {} clk1M_1 {} clk500K_1 {} clk10K_1 {} \process4:cnt[2] {} } { 0.000ns 0.000ns 1.738ns 0.866ns 4.453ns 3.051ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } {  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } {  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.079 ns" { \process4:cnt[2] Add2~90 Add2~94 Add2~95 \process4:cnt[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.079 ns" { \process4:cnt[2] {} Add2~90 {} Add2~94 {} Add2~95 {} \process4:cnt[4] {} } { 0.000ns 1.293ns 0.000ns 0.000ns 0.768ns } { 0.000ns 0.978ns 0.261ns 0.975ns 0.804ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.071 ns" { clk50M clk1M_1 clk500K_1 clk10K_1 \process4:cnt[4] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.071 ns" { clk50M {} clk50M~combout {} clk1M_1 {} clk500K_1 {} clk10K_1 {} \process4:cnt[4] {} } { 0.000ns 0.000ns 1.738ns 0.866ns 4.453ns 3.051ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.071 ns" { clk50M clk1M_1 clk500K_1 clk10K_1 \process4:cnt[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.071 ns" { clk50M {} clk50M~combout {} clk1M_1 {} clk500K_1 {} clk10K_1 {} \process4:cnt[2] {} } { 0.000ns 0.000ns 1.738ns 0.866ns 4.453ns 3.051ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk50M clk100 clk100_1 20.712 ns register " "Info: tco from clock \"clk50M\" to destination pin \"clk100\" through register \"clk100_1\" is 20.712 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk50M source 16.071 ns + Longest register " "Info: + Longest clock path from clock \"clk50M\" to source register is 16.071 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk50M 1 CLK PIN_18 6 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk50M'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk50M } "NODE_NAME" } } { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clk1M_1 2 REG LC_X10_Y4_N2 3 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y4_N2; Fanout = 3; REG Node = 'clk1M_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk50M clk1M_1 } "NODE_NAME" } } { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.866 ns) + CELL(1.294 ns) 6.355 ns clk500K_1 3 REG LC_X10_Y4_N7 8 " "Info: 3: + IC(0.866 ns) + CELL(1.294 ns) = 6.355 ns; Loc. = LC_X10_Y4_N7; Fanout = 8; REG Node = 'clk500K_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.160 ns" { clk1M_1 clk500K_1 } "NODE_NAME" } } { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.453 ns) + CELL(1.294 ns) 12.102 ns clk10K_1 4 REG LC_X12_Y3_N2 9 " "Info: 4: + IC(4.453 ns) + CELL(1.294 ns) = 12.102 ns; Loc. = LC_X12_Y3_N2; Fanout = 9; REG Node = 'clk10K_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.747 ns" { clk500K_1 clk10K_1 } "NODE_NAME" } } { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.051 ns) + CELL(0.918 ns) 16.071 ns clk100_1 5 REG LC_X14_Y9_N2 2 " "Info: 5: + IC(3.051 ns) + CELL(0.918 ns) = 16.071 ns; Loc. = LC_X14_Y9_N2; Fanout = 2; REG Node = 'clk100_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.969 ns" { clk10K_1 clk100_1 } "NODE_NAME" } } { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.963 ns ( 37.10 % ) " "Info: Total cell delay = 5.963 ns ( 37.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.108 ns ( 62.90 % ) " "Info: Total interconnect delay = 10.108 ns ( 62.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.071 ns" { clk50M clk1M_1 clk500K_1 clk10K_1 clk100_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.071 ns" { clk50M {} clk50M~combout {} clk1M_1 {} clk500K_1 {} clk10K_1 {} clk100_1 {} } { 0.000ns 0.000ns 1.738ns 0.866ns 4.453ns 3.051ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 48 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.265 ns + Longest register pin " "Info: + Longest register to pin delay is 4.265 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk100_1 1 REG LC_X14_Y9_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y9_N2; Fanout = 2; REG Node = 'clk100_1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk100_1 } "NODE_NAME" } } { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.943 ns) + CELL(2.322 ns) 4.265 ns clk100 2 PIN PIN_112 0 " "Info: 2: + IC(1.943 ns) + CELL(2.322 ns) = 4.265 ns; Loc. = PIN_112; Fanout = 0; PIN Node = 'clk100'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.265 ns" { clk100_1 clk100 } "NODE_NAME" } } { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 54.44 % ) " "Info: Total cell delay = 2.322 ns ( 54.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.943 ns ( 45.56 % ) " "Info: Total interconnect delay = 1.943 ns ( 45.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.265 ns" { clk100_1 clk100 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.265 ns" { clk100_1 {} clk100 {} } { 0.000ns 1.943ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "16.071 ns" { clk50M clk1M_1 clk500K_1 clk10K_1 clk100_1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "16.071 ns" { clk50M {} clk50M~combout {} clk1M_1 {} clk500K_1 {} clk10K_1 {} clk100_1 {} } { 0.000ns 0.000ns 1.738ns 0.866ns 4.453ns 3.051ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.918ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.265 ns" { clk100_1 clk100 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.265 ns" { clk100_1 {} clk100 {} } { 0.000ns 1.943ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "113 " "Info: Allocated 113 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 06 10:05:24 2009 " "Info: Processing ended: Fri Mar 06 10:05:24 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}