prev_cmp_clk_div.map.qmsg

VHDL语言描述

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 06 10:04:19 2009 " "Info: Processing started: Fri Mar 06 10:04:19 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off clk_div -c clk_div " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clk_div -c clk_div" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_div.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clk_div.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clk_div-bhv " "Info: Found design unit 1: clk_div-bhv" {  } { { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 clk_div " "Info: Found entity 1: clk_div" {  } { { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_INT_TYPE_MISMATCH" "std_logic_vector clk_div.vhd(21) " "Error (10517): VHDL type mismatch error at clk_div.vhd(21): std_logic_vector type does not match integer literal" {  } { { "clk_div.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/mywork/clk_div/clk_div.vhd" 21 0 0 } }  } 0 10517 "VHDL type mismatch error at %2!s!: %1!s! type does not match integer literal" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "152 " "Info: Allocated 152 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Fri Mar 06 10:04:21 2009 " "Error: Processing ended: Fri Mar 06 10:04:21 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}