clk_div.fit.summary

来自「VHDL语言描述」· SUMMARY 代码 · 共 12 行

Fitter Status : Successful - Fri Mar 06 10:05:13 2009
Quartus II Version : 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
Revision Name : clk_div
Top-level Entity Name : clk_div
Family : MAX II
Device : EPM1270T144C5
Timing Models : Final
Total logic elements : 36 / 1,270 ( 3 % )
Total pins : 5 / 116 ( 4 % )
Total virtual pins : 0
UFM blocks : 0 / 1 ( 0 % )