clk_div.tan.rpt

VHDL语言描述

; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; \process3:cnt[4] ; clk10K_1         ; clk50M     ; clk50M   ; None                        ; None                      ; 1.882 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; clk500K_1        ; clk500K_1        ; clk50M     ; clk50M   ; None                        ; None                      ; 1.753 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; \process3:cnt[4] ; \process3:cnt[0] ; clk50M     ; clk50M   ; None                        ; None                      ; 1.553 ns                ;
; N/A   ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; cnt[4]           ; cnt[0]           ; clk50M     ; clk50M   ; None                        ; None                      ; 1.552 ns                ;
+-------+------------------------------------------------+------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------------+
; tco                                                                  ;
+-------+--------------+------------+-----------+---------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To      ; From Clock ;
+-------+--------------+------------+-----------+---------+------------+
; N/A   ; None         ; 20.712 ns  ; clk100_1  ; clk100  ; clk50M     ;
; N/A   ; None         ; 18.157 ns  ; clk10K_1  ; clk10K  ; clk50M     ;
; N/A   ; None         ; 9.445 ns   ; clk500K_1 ; clk500K ; clk50M     ;
; N/A   ; None         ; 9.168 ns   ; clk1M_1   ; clk1M   ; clk50M     ;
+-------+--------------+------------+-----------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Fri Mar 06 10:05:22 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clk_div -c clk_div
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk50M" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "clk500K_1" as buffer
    Info: Detected ripple clock "clk10K_1" as buffer
    Info: Detected ripple clock "clk1M_1" as buffer
Info: Clock "clk50M" has Internal fmax of 172.77 MHz between source register "\process4:cnt[2]" and destination register "\process4:cnt[4]" (period= 5.788 ns)
    Info: + Longest register to register delay is 5.079 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X13_Y10_N0; Fanout = 4; REG Node = '\process4:cnt[2]'
        Info: 2: + IC(1.293 ns) + CELL(0.978 ns) = 2.271 ns; Loc. = LC_X14_Y10_N3; Fanout = 2; COMB Node = 'Add2~90'
        Info: 3: + IC(0.000 ns) + CELL(0.261 ns) = 2.532 ns; Loc. = LC_X14_Y10_N4; Fanout = 2; COMB Node = 'Add2~94'
        Info: 4: + IC(0.000 ns) + CELL(0.975 ns) = 3.507 ns; Loc. = LC_X14_Y10_N5; Fanout = 1; COMB Node = 'Add2~95'
        Info: 5: + IC(0.768 ns) + CELL(0.804 ns) = 5.079 ns; Loc. = LC_X14_Y10_N9; Fanout = 7; REG Node = '\process4:cnt[4]'
        Info: Total cell delay = 3.018 ns ( 59.42 % )
        Info: Total interconnect delay = 2.061 ns ( 40.58 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk50M" to destination register is 16.071 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk50M'
            Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y4_N2; Fanout = 3; REG Node = 'clk1M_1'
            Info: 3: + IC(0.866 ns) + CELL(1.294 ns) = 6.355 ns; Loc. = LC_X10_Y4_N7; Fanout = 8; REG Node = 'clk500K_1'
            Info: 4: + IC(4.453 ns) + CELL(1.294 ns) = 12.102 ns; Loc. = LC_X12_Y3_N2; Fanout = 9; REG Node = 'clk10K_1'
            Info: 5: + IC(3.051 ns) + CELL(0.918 ns) = 16.071 ns; Loc. = LC_X14_Y10_N9; Fanout = 7; REG Node = '\process4:cnt[4]'
            Info: Total cell delay = 5.963 ns ( 37.10 % )
            Info: Total interconnect delay = 10.108 ns ( 62.90 % )
        Info: - Longest clock path from clock "clk50M" to source register is 16.071 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk50M'
            Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y4_N2; Fanout = 3; REG Node = 'clk1M_1'
            Info: 3: + IC(0.866 ns) + CELL(1.294 ns) = 6.355 ns; Loc. = LC_X10_Y4_N7; Fanout = 8; REG Node = 'clk500K_1'
            Info: 4: + IC(4.453 ns) + CELL(1.294 ns) = 12.102 ns; Loc. = LC_X12_Y3_N2; Fanout = 9; REG Node = 'clk10K_1'
            Info: 5: + IC(3.051 ns) + CELL(0.918 ns) = 16.071 ns; Loc. = LC_X13_Y10_N0; Fanout = 4; REG Node = '\process4:cnt[2]'
            Info: Total cell delay = 5.963 ns ( 37.10 % )
            Info: Total interconnect delay = 10.108 ns ( 62.90 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
Info: tco from clock "clk50M" to destination pin "clk100" through register "clk100_1" is 20.712 ns
    Info: + Longest clock path from clock "clk50M" to source register is 16.071 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 6; CLK Node = 'clk50M'
        Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X10_Y4_N2; Fanout = 3; REG Node = 'clk1M_1'
        Info: 3: + IC(0.866 ns) + CELL(1.294 ns) = 6.355 ns; Loc. = LC_X10_Y4_N7; Fanout = 8; REG Node = 'clk500K_1'
        Info: 4: + IC(4.453 ns) + CELL(1.294 ns) = 12.102 ns; Loc. = LC_X12_Y3_N2; Fanout = 9; REG Node = 'clk10K_1'
        Info: 5: + IC(3.051 ns) + CELL(0.918 ns) = 16.071 ns; Loc. = LC_X14_Y9_N2; Fanout = 2; REG Node = 'clk100_1'
        Info: Total cell delay = 5.963 ns ( 37.10 % )
        Info: Total interconnect delay = 10.108 ns ( 62.90 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 4.265 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X14_Y9_N2; Fanout = 2; REG Node = 'clk100_1'
        Info: 2: + IC(1.943 ns) + CELL(2.322 ns) = 4.265 ns; Loc. = PIN_112; Fanout = 0; PIN Node = 'clk100'
        Info: Total cell delay = 2.322 ns ( 54.44 % )
        Info: Total interconnect delay = 1.943 ns ( 45.56 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 113 megabytes of memory during processing
    Info: Processing ended: Fri Mar 06 10:05:24 2009
    Info: Elapsed time: 00:00:02