fp1.vhd

来自「基于vhdl的qpsk算法研究与性能测试」· VHDL 代码 · 共 30 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fp1 IS
   PORT(
        CP :IN STD_LOGIC;
        CLK,CD,CW :OUT STD_LOGIC
        );
END fp1;
ARCHITECTURE a OF fp1 IS
SIGNAL TEMP :STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL TEM  :STD_LOGIC_VECTOR(12 DOWNTO 0);
BEGIN
PROCESS (CP)
BEGIN
IF(CP'EVENT AND CP='1') THEN
IF TEMP="1111111111111" THEN 
TEMP<="0000000000000";
ELSE TEMP<=TEMP+1;
     TEM<=TEMP+2;
END IF;
END IF;
END PROCESS;
CLK<=TEMP(1);
CD<=TEMP(2);
CW<=TEM(1);
END a;