add1.rpt

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** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                     Logic cells placed in LAB 'B'
        +--------------------------- LC26 DS0
        | +------------------------- LC27 DS1
        | | +----------------------- LC28 DS2
        | | | +--------------------- LC30 DS3
        | | | | +------------------- LC25 DS4
        | | | | | +----------------- LC24 DS5
        | | | | | | +--------------- LC17 DS6
        | | | | | | | +------------- LC18 DS7
        | | | | | | | | +----------- LC19 DS8
        | | | | | | | | | +--------- LC20 DS9
        | | | | | | | | | | +------- LC21 DS10
        | | | | | | | | | | | +----- LC22 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|cout_node
        | | | | | | | | | | | | +--- LC23 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|gcp2
        | | | | | | | | | | | | | +- LC29 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|g4
        | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC22 -> - - - - - - - - * * * - - - | - * | <-- |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|cout_node
LC23 -> - - - * - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|gcp2
LC29 -> - - - - * * - - - - - - - - | - * | <-- |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|g4

Pin
4    -> * * * - - - * * - - - * * * | - * | <-- B0
16   -> - * * - - - * * - - - * * * | - * | <-- B1
14   -> - - * - - - * * - - - * * * | - * | <-- B2
13   -> - - - * - - * * - - - * - * | - * | <-- B3
12   -> - - - - * * * * - - - * - - | - * | <-- B4
11   -> - - - - - * * * - - - * - - | - * | <-- B5
9    -> - - - - - - * * - - - * - - | - * | <-- B6
8    -> - - - - - - - * - - - * - - | - * | <-- B7
7    -> - - - - - - - - * * * - - - | - * | <-- B8
6    -> - - - - - - - - - * * - - - | - * | <-- B9
5    -> - - - - - - - - - - * - - - | - * | <-- B10


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                 e:\vhdcx\add1.rpt
add1

** EQUATIONS **

B0       : INPUT;
B1       : INPUT;
B2       : INPUT;
B3       : INPUT;
B4       : INPUT;
B5       : INPUT;
B6       : INPUT;
B7       : INPUT;
B8       : INPUT;
B9       : INPUT;
B10      : INPUT;

-- Node name is 'DS0' 
-- Equation name is 'DS0', location is LC026, type is output.
 DS0     = LCELL(!B0 $  GND);

-- Node name is 'DS1' 
-- Equation name is 'DS1', location is LC027, type is output.
 DS1     = LCELL(!B1 $  B0);

-- Node name is 'DS2' 
-- Equation name is 'DS2', location is LC028, type is output.
 DS2     = LCELL(!B2 $  _EQ001);
  _EQ001 = !B0 & !B1;

-- Node name is 'DS3' 
-- Equation name is 'DS3', location is LC030, type is output.
 DS3     = LCELL( B3 $  _LC023);

-- Node name is 'DS4' 
-- Equation name is 'DS4', location is LC025, type is output.
 DS4     = LCELL( B4 $  _LC029);

-- Node name is 'DS5' 
-- Equation name is 'DS5', location is LC024, type is output.
 DS5     = LCELL( B5 $  _EQ002);
  _EQ002 =  B4 &  _LC029;

-- Node name is 'DS6' 
-- Equation name is 'DS6', location is LC017, type is output.
 DS6     = LCELL( _EQ003 $  B6);
  _EQ003 =  B1 &  B2 &  B3 &  B4 &  B5
         #  B0 &  B2 &  B3 &  B4 &  B5;

-- Node name is 'DS7' 
-- Equation name is 'DS7', location is LC018, type is output.
 DS7     = LCELL( _EQ004 $  B7);
  _EQ004 =  B1 &  B2 &  B3 &  B4 &  B5 &  B6
         #  B0 &  B2 &  B3 &  B4 &  B5 &  B6;

-- Node name is 'DS8' 
-- Equation name is 'DS8', location is LC019, type is output.
 DS8     = LCELL( B8 $  _LC022);

-- Node name is 'DS9' 
-- Equation name is 'DS9', location is LC020, type is output.
 DS9     = LCELL( B9 $  _EQ005);
  _EQ005 =  B8 &  _LC022;

-- Node name is 'DS10' 
-- Equation name is 'DS10', location is LC021, type is output.
 DS10    = LCELL( B10 $  _EQ006);
  _EQ006 =  B8 &  B9 &  _LC022;

-- Node name is '|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|cout_node' from file "addcore.tdf" line 165, column 5
-- Equation name is '_LC022', type is buried 
_LC022   = LCELL( _EQ007 $  GND);
  _EQ007 =  B0 &  B2 &  B3 &  B4 &  B5 &  B6 &  B7
         #  B1 &  B2 &  B3 &  B4 &  B5 &  B6 &  B7;

-- Node name is '|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC023', type is buried 
_LC023   = LCELL( _EQ008 $  B2);
  _EQ008 = !B0 & !B1 &  B2;

-- Node name is '|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC029', type is buried 
_LC029   = LCELL( _EQ009 $  GND);
  _EQ009 =  B1 &  B2 &  B3
         #  B0 &  B2 &  B3;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                          e:\vhdcx\add1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 18,195K