add1.rpt
来自「基于vhdl的qpsk算法研究与性能测试」· RPT 代码 · 共 463 行 · 第 1/2 页
RPT
463 行
Project Information e:\vhdcx\add1.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 10/30/2008 09:18:55
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
ADD1
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
add1 EPM7032LC44-6 11 11 0 14 0 43 %
User Pins: 11 11 0
Project Information e:\vhdcx\add1.rpt
** FILE HIERARCHY **
|lpm_add_sub:56|
|lpm_add_sub:56|addcore:adder|
|lpm_add_sub:56|addcore:adder|addcore:adder1|
|lpm_add_sub:56|addcore:adder|addcore:adder0|
|lpm_add_sub:56|altshift:result_ext_latency_ffs|
|lpm_add_sub:56|altshift:carry_ext_latency_ffs|
|lpm_add_sub:56|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\vhdcx\add1.rpt
add1
***** Logic for device 'add1' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
B V G G G G G D D
B 1 B C N N N N N S S
9 0 0 C D D D D D 6 7
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
B8 | 7 39 | DS8
B7 | 8 38 | DS9
B6 | 9 37 | DS10
GND | 10 36 | RESERVED
B5 | 11 35 | VCC
B4 | 12 EPM7032LC44-6 34 | RESERVED
B3 | 13 33 | DS5
B2 | 14 32 | DS4
VCC | 15 31 | DS0
B1 | 16 30 | GND
RESERVED | 17 29 | DS1
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R D R D
E E E E N C E E S E S
S S S S D C S S 3 S 2
E E E E E E E
R R R R R R R
V V V V V V V
E E E E E E E
D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\vhdcx\add1.rpt
add1
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 11/16( 68%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 14/16( 87%) 11/16( 68%) 0/16( 0%) 14/36( 38%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 22/32 ( 68%)
Total logic cells used: 14/32 ( 43%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 14/32 ( 43%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 3.71
Total fan-in: 52
Total input pins required: 11
Total output pins required: 11
Total bidirectional pins required: 0
Total logic cells required: 14
Total flipflops required: 0
Total product terms required: 29
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: e:\vhdcx\add1.rpt
add1
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 5 3 B0
16 (11) (A) INPUT 0 0 0 0 0 4 3 B1
14 (10) (A) INPUT 0 0 0 0 0 3 3 B2
13 (9) (A) INPUT 0 0 0 0 0 3 2 B3
12 (8) (A) INPUT 0 0 0 0 0 4 1 B4
11 (7) (A) INPUT 0 0 0 0 0 3 1 B5
9 (6) (A) INPUT 0 0 0 0 0 2 1 B6
8 (5) (A) INPUT 0 0 0 0 0 1 1 B7
7 (4) (A) INPUT 0 0 0 0 0 3 0 B8
6 (3) (A) INPUT 0 0 0 0 0 2 0 B9
5 (2) (A) INPUT 0 0 0 0 0 1 0 B10
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\vhdcx\add1.rpt
add1
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
31 26 B OUTPUT t 0 0 0 1 0 0 0 DS0
29 27 B OUTPUT t 0 0 0 2 0 0 0 DS1
28 28 B OUTPUT t 0 0 0 3 0 0 0 DS2
26 30 B OUTPUT t 0 0 0 1 1 0 0 DS3
32 25 B OUTPUT t 0 0 0 1 1 0 0 DS4
33 24 B OUTPUT t 0 0 0 2 1 0 0 DS5
41 17 B OUTPUT t 0 0 0 7 0 0 0 DS6
40 18 B OUTPUT t 0 0 0 8 0 0 0 DS7
39 19 B OUTPUT t 0 0 0 1 1 0 0 DS8
38 20 B OUTPUT t 0 0 0 2 1 0 0 DS9
37 21 B OUTPUT t 0 0 0 3 1 0 0 DS10
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\vhdcx\add1.rpt
add1
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(36) 22 B SOFT t 0 0 0 8 0 3 0 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|cout_node
(34) 23 B SOFT t 0 0 0 3 0 1 0 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|gcp2
(27) 29 B SOFT t 0 0 0 4 0 2 0 |LPM_ADD_SUB:56|addcore:adder|addcore:adder0|g4
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\vhdcx\add1.rpt
add1
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