pianyi.rpt

基于vhdl的qpsk算法研究与性能测试

Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                               e:\vhdcx\pianyi.rpt
pianyi

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                       Logic cells placed in LAB 'B'
        +----------------------------- LC28 QO0
        | +--------------------------- LC29 QO1
        | | +------------------------- LC30 QO2
        | | | +----------------------- LC31 QO3
        | | | | +--------------------- LC27 QO4
        | | | | | +------------------- LC17 QO5
        | | | | | | +----------------- LC25 Q11
        | | | | | | | +--------------- LC24 A7
        | | | | | | | | +------------- LC23 A6
        | | | | | | | | | +----------- LC22 A5
        | | | | | | | | | | +--------- LC21 A4
        | | | | | | | | | | | +------- LC20 A3
        | | | | | | | | | | | | +----- LC19 A2
        | | | | | | | | | | | | | +--- LC18 A1
        | | | | | | | | | | | | | | +- LC26 A0
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC17 -> - - - - * - - - - - - - - - - | - * | <-- QO5
LC25 -> - - - - * - - - - - - - - - - | - * | <-- Q11
LC24 -> - - - - - - - - - * - - - - - | - * | <-- A7
LC23 -> - - - - - - - - - - * - - - - | - * | <-- A6
LC22 -> - - - - - - - - - - - * - - - | - * | <-- A5
LC21 -> - - - - - - - - - - - - * - - | - * | <-- A4
LC20 -> - - - - - - - - - - - - - * - | - * | <-- A3
LC19 -> - - - - - - - - - - - - - - * | - * | <-- A2
LC18 -> - - - - - - * * - - - - - - - | - * | <-- A1
LC26 -> - - - - - * - - * - - - - - - | - * | <-- A0

Pin
43   -> - - - - - - - - - - - - - - - | - - | <-- CP


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               e:\vhdcx\pianyi.rpt
pianyi

** EQUATIONS **

CP       : INPUT;

-- Node name is ':23' = 'A0' 
-- Equation name is 'A0', location is LC026, type is buried.
A0       = DFFE( A2 $  GND, GLOBAL( CP),  VCC,  VCC,  VCC);

-- Node name is ':22' = 'A1' 
-- Equation name is 'A1', location is LC018, type is buried.
A1       = DFFE( A3 $  GND, GLOBAL( CP),  VCC,  VCC,  VCC);

-- Node name is ':21' = 'A2' 
-- Equation name is 'A2', location is LC019, type is buried.
A2       = DFFE( A4 $  GND, GLOBAL( CP),  VCC,  VCC,  VCC);

-- Node name is ':20' = 'A3' 
-- Equation name is 'A3', location is LC020, type is buried.
A3       = DFFE( A5 $  GND, GLOBAL( CP),  VCC,  VCC,  VCC);

-- Node name is ':19' = 'A4' 
-- Equation name is 'A4', location is LC021, type is buried.
A4       = DFFE( A6 $  GND, GLOBAL( CP),  VCC,  VCC,  VCC);

-- Node name is ':18' = 'A5' 
-- Equation name is 'A5', location is LC022, type is buried.
A5       = DFFE( A7 $  GND, GLOBAL( CP),  VCC,  VCC,  VCC);

-- Node name is ':17' = 'A6' 
-- Equation name is 'A6', location is LC023, type is buried.
A6       = DFFE( A0 $  GND, GLOBAL( CP),  VCC,  VCC,  VCC);

-- Node name is ':16' = 'A7' 
-- Equation name is 'A7', location is LC024, type is buried.
A7       = DFFE( A1 $  GND, GLOBAL( CP),  VCC,  VCC,  VCC);

-- Node name is 'QO0' 
-- Equation name is 'QO0', location is LC028, type is output.
 QO0     = LCELL( VCC $  VCC);

-- Node name is 'QO1' 
-- Equation name is 'QO1', location is LC029, type is output.
 QO1     = LCELL( VCC $  VCC);

-- Node name is 'QO2' 
-- Equation name is 'QO2', location is LC030, type is output.
 QO2     = LCELL( VCC $  VCC);

-- Node name is 'QO3' 
-- Equation name is 'QO3', location is LC031, type is output.
 QO3     = LCELL( GND $  VCC);

-- Node name is 'QO4' 
-- Equation name is 'QO4', location is LC027, type is output.
 QO4     = LCELL(!QO5 $  Q11);

-- Node name is 'QO5' = 'Q10' 
-- Equation name is 'QO5', location is LC017, type is output.
 QO5     = DFFE( A0 $  GND, GLOBAL( CP),  VCC,  VCC,  VCC);

-- Node name is ':14' = 'Q11' 
-- Equation name is 'Q11', location is LC025, type is buried.
Q11      = DFFE( A1 $  GND, GLOBAL( CP),  VCC,  VCC,  VCC);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        e:\vhdcx\pianyi.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,938K