📄 suocun.rpt
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Project Information e:\vhdcx\suocun.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 10/29/2008 13:58:09
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
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the intellectual property, including patents, copyrights, trademarks,
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***** Project compilation was successful
SUOCUN
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
suocun EPM7032LC44-6 19 17 0 17 0 53 %
User Pins: 19 17 0
Device-Specific Information: e:\vhdcx\suocun.rpt
suocun
***** Logic for device 'suocun' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Device-Specific Information: e:\vhdcx\suocun.rpt
suocun
** ERROR SUMMARY **
Info: Chip 'suocun' in device 'EPM7032LC44-6' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
A A A
D D D
I D I I I D D
N C R V N N N G R R
2 L 2 C L 2 3 3 N 1 2
0 K 0 C D 9 0 1 D 1 3
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
IN21 | 7 39 | ADDR210
IN22 | 8 38 | ADDR29
IN23 | 9 37 | ADDR24
GND | 10 36 | ADDR28
IN24 | 11 35 | VCC
IN25 | 12 EPM7032LC44-6 34 | ADDR27
IN26 | 13 33 | ADDR26
IN27 | 14 32 | ADDR10
VCC | 15 31 | ADDR22
IN28 | 16 30 | GND
IN210 | 17 29 | ADDR21
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
I I I I G V A A A A A
N N N N N C D D D D D
3 3 3 3 D C D D D D D
5 4 3 2 R R R R R
1 1 1 1 2
2 3 4 5 5
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\vhdcx\suocun.rpt
suocun
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 1/16( 6%) 16/16(100%) 0/16( 0%) 3/36( 8%)
B: LC17 - LC32 16/16(100%) 16/16(100%) 0/16( 0%) 18/36( 50%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 32/32 (100%)
Total logic cells used: 17/32 ( 53%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 17/32 ( 53%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 3.70
Total fan-in: 63
Total input pins required: 19
Total output pins required: 17
Total bidirectional pins required: 0
Total logic cells required: 17
Total flipflops required: 17
Total product terms required: 46
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: e:\vhdcx\suocun.rpt
suocun
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
5 (2) (A) INPUT 0 0 0 0 0 17 0 CLK
6 (3) (A) INPUT 0 0 0 0 0 1 0 IN20
7 (4) (A) INPUT 0 0 0 0 0 1 0 IN21
8 (5) (A) INPUT 0 0 0 0 0 1 0 IN22
9 (6) (A) INPUT 0 0 0 0 0 1 0 IN23
11 (7) (A) INPUT 0 0 0 0 0 1 0 IN24
12 (8) (A) INPUT 0 0 0 0 0 2 0 IN25
13 (9) (A) INPUT 0 0 0 0 0 2 0 IN26
14 (10) (A) INPUT 0 0 0 0 0 2 0 IN27
16 (11) (A) INPUT 0 0 0 0 0 2 0 IN28
1 - - INPUT 0 0 0 0 0 2 0 IN29
44 - - INPUT 0 0 0 0 0 2 0 IN30
43 - - INPUT 0 0 0 0 0 2 0 IN31
21 (16) (A) INPUT 0 0 0 0 0 2 0 IN32
20 (15) (A) INPUT 0 0 0 0 0 2 0 IN33
19 (14) (A) INPUT 0 0 0 0 0 2 0 IN34
18 (13) (A) INPUT 0 0 0 0 0 2 0 IN35
17 (12) (A) INPUT 0 0 0 0 0 2 0 IN210
2 - - INPUT 0 0 0 0 0 17 0 LD
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\vhdcx\suocun.rpt
suocun
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
32 25 B FF t 0 0 0 4 0 0 0 ADDR10 (:42)
41 17 B FF t 0 0 0 4 0 0 0 ADDR11 (:41)
24 32 B FF t 0 0 0 4 0 0 0 ADDR12 (:40)
25 31 B FF t 0 0 0 4 0 0 0 ADDR13 (:39)
26 30 B FF t 0 0 0 4 0 0 0 ADDR14 (:38)
27 29 B FF t 0 0 0 4 0 0 0 ADDR15 (:37)
4 1 A FF t 0 0 0 3 0 0 0 ADDR20 (:47)
29 27 B FF t 0 0 0 3 0 0 0 ADDR21 (:46)
31 26 B FF t 0 0 0 3 0 0 0 ADDR22 (:45)
40 18 B FF t 0 0 0 3 0 0 0 ADDR23 (:44)
37 21 B FF t 0 0 0 3 0 0 0 ADDR24 (:43)
28 28 B FF t 0 0 0 4 0 0 0 ADDR25 (~42~1)
33 24 B FF t 0 0 0 4 0 0 0 ADDR26 (~41~1)
34 23 B FF t 0 0 0 4 0 0 0 ADDR27 (~40~1)
36 22 B FF t 0 0 0 4 0 0 0 ADDR28 (~39~1)
38 20 B FF t 0 0 0 4 0 0 0 ADDR29 (~38~1)
39 19 B FF t 0 0 0 4 0 0 0 ADDR210 (~37~1)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\vhdcx\suocun.rpt
suocun
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+- LC1 ADDR20
|
| Other LABs fed by signals
| that feed LAB 'A'
LC | | A B | Logic cells that feed LAB 'A':
Pin
5 -> * | * * | <-- CLK
6 -> * | * - | <-- IN20
1 -> - | - * | <-- IN29
44 -> - | - * | <-- IN30
43 -> - | - * | <-- IN31
2 -> * | * * | <-- LD
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\vhdcx\suocun.rpt
suocun
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC25 ADDR10
| +----------------------------- LC17 ADDR11
| | +--------------------------- LC32 ADDR12
| | | +------------------------- LC31 ADDR13
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