📄 suocunf.rpt
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| | | | +----------------------- LC30 ADDR14
| | | | | +--------------------- LC29 ADDR15
| | | | | | +------------------- LC27 ADDR21
| | | | | | | +----------------- LC26 ADDR22
| | | | | | | | +--------------- LC18 ADDR23
| | | | | | | | | +------------- LC21 ADDR24
| | | | | | | | | | +----------- LC28 ADDR25
| | | | | | | | | | | +--------- LC24 ADDR26
| | | | | | | | | | | | +------- LC23 ADDR27
| | | | | | | | | | | | | +----- LC22 ADDR28
| | | | | | | | | | | | | | +--- LC20 ADDR29
| | | | | | | | | | | | | | | +- LC19 ADDR210
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
Pin
5 -> * * * * * * * * * * * * * * * * | * * | <-- CLK
7 -> - - - - - - * - - - - - - - - - | - * | <-- IN21
8 -> - - - - - - - * - - - - - - - - | - * | <-- IN22
9 -> - - - - - - - - * - - - - - - - | - * | <-- IN23
11 -> - - - - - - - - - * - - - - - - | - * | <-- IN24
12 -> * - - - - - - - - - * - - - - - | - * | <-- IN25
13 -> - * - - - - - - - - - * - - - - | - * | <-- IN26
14 -> - - * - - - - - - - - - * - - - | - * | <-- IN27
16 -> - - - * - - - - - - - - - * - - | - * | <-- IN28
1 -> - - - - * - - - - - - - - - * - | - * | <-- IN29
44 -> * - - - - - - - - - * - - - - - | - * | <-- IN30
43 -> - * - - - - - - - - - * - - - - | - * | <-- IN31
21 -> - - * - - - - - - - - - * - - - | - * | <-- IN32
20 -> - - - * - - - - - - - - - * - - | - * | <-- IN33
19 -> - - - - * - - - - - - - - - * - | - * | <-- IN34
18 -> - - - - - * - - - - - - - - - * | - * | <-- IN35
17 -> - - - - - * - - - - - - - - - * | - * | <-- IN210
2 -> * * * * * * * * * * * * * * * * | * * | <-- LD
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\vhdcx\suocunf.rpt
suocunf
** EQUATIONS **
CLK : INPUT;
IN20 : INPUT;
IN21 : INPUT;
IN22 : INPUT;
IN23 : INPUT;
IN24 : INPUT;
IN25 : INPUT;
IN26 : INPUT;
IN27 : INPUT;
IN28 : INPUT;
IN29 : INPUT;
IN30 : INPUT;
IN31 : INPUT;
IN32 : INPUT;
IN33 : INPUT;
IN34 : INPUT;
IN35 : INPUT;
IN210 : INPUT;
LD : INPUT;
-- Node name is 'ADDR10' = 'SAV5'
-- Equation name is 'ADDR10', location is LC025, type is output.
ADDR10 = DFFE( _EQ001 $ GND, !CLK, VCC, VCC, VCC);
_EQ001 = IN25 & LD
# IN30 & !LD;
-- Node name is 'ADDR11' = 'SAV6'
-- Equation name is 'ADDR11', location is LC017, type is output.
ADDR11 = DFFE( _EQ002 $ GND, !CLK, VCC, VCC, VCC);
_EQ002 = IN26 & LD
# IN31 & !LD;
-- Node name is 'ADDR12' = 'SAV7'
-- Equation name is 'ADDR12', location is LC032, type is output.
ADDR12 = DFFE( _EQ003 $ GND, !CLK, VCC, VCC, VCC);
_EQ003 = IN27 & LD
# IN32 & !LD;
-- Node name is 'ADDR13' = 'SAV8'
-- Equation name is 'ADDR13', location is LC031, type is output.
ADDR13 = DFFE( _EQ004 $ GND, !CLK, VCC, VCC, VCC);
_EQ004 = IN28 & LD
# IN33 & !LD;
-- Node name is 'ADDR14' = 'SAV9'
-- Equation name is 'ADDR14', location is LC030, type is output.
ADDR14 = DFFE( _EQ005 $ GND, !CLK, VCC, VCC, VCC);
_EQ005 = IN29 & LD
# IN34 & !LD;
-- Node name is 'ADDR15' = 'SAV10'
-- Equation name is 'ADDR15', location is LC029, type is output.
ADDR15 = DFFE( _EQ006 $ GND, !CLK, VCC, VCC, VCC);
_EQ006 = IN210 & LD
# IN35 & !LD;
-- Node name is 'ADDR20' = 'SAV0'
-- Equation name is 'ADDR20', location is LC001, type is output.
ADDR20 = DFFE( _EQ007 $ GND, !CLK, VCC, VCC, VCC);
_EQ007 = IN20 & LD;
-- Node name is 'ADDR21' = 'SAV1'
-- Equation name is 'ADDR21', location is LC027, type is output.
ADDR21 = DFFE( _EQ008 $ GND, !CLK, VCC, VCC, VCC);
_EQ008 = IN21 & LD;
-- Node name is 'ADDR22' = 'SAV2'
-- Equation name is 'ADDR22', location is LC026, type is output.
ADDR22 = DFFE( _EQ009 $ GND, !CLK, VCC, VCC, VCC);
_EQ009 = IN22 & LD;
-- Node name is 'ADDR23' = 'SAV3'
-- Equation name is 'ADDR23', location is LC018, type is output.
ADDR23 = DFFE( _EQ010 $ GND, !CLK, VCC, VCC, VCC);
_EQ010 = IN23 & LD;
-- Node name is 'ADDR24' = 'SAV4'
-- Equation name is 'ADDR24', location is LC021, type is output.
ADDR24 = DFFE( _EQ011 $ GND, !CLK, VCC, VCC, VCC);
_EQ011 = IN24 & LD;
-- Node name is 'ADDR25' = 'SAV5~1'
-- Equation name is 'ADDR25', location is LC028, type is output.
ADDR25 = DFFE( _EQ001 $ GND, !CLK, VCC, VCC, VCC);
-- Node name is 'ADDR26' = 'SAV6~1'
-- Equation name is 'ADDR26', location is LC024, type is output.
ADDR26 = DFFE( _EQ002 $ GND, !CLK, VCC, VCC, VCC);
-- Node name is 'ADDR27' = 'SAV7~1'
-- Equation name is 'ADDR27', location is LC023, type is output.
ADDR27 = DFFE( _EQ003 $ GND, !CLK, VCC, VCC, VCC);
-- Node name is 'ADDR28' = 'SAV8~1'
-- Equation name is 'ADDR28', location is LC022, type is output.
ADDR28 = DFFE( _EQ004 $ GND, !CLK, VCC, VCC, VCC);
-- Node name is 'ADDR29' = 'SAV9~1'
-- Equation name is 'ADDR29', location is LC020, type is output.
ADDR29 = DFFE( _EQ005 $ GND, !CLK, VCC, VCC, VCC);
-- Node name is 'ADDR210' = 'SAV10~1'
-- Equation name is 'ADDR210', location is LC019, type is output.
ADDR210 = DFFE( _EQ006 $ GND, !CLK, VCC, VCC, VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\vhdcx\suocunf.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,073K
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