add1.vhd

来自「基于vhdl的qpsk算法研究与性能测试」· VHDL 代码 · 共 19 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADD1 IS
   PORT(
        B :IN STD_LOGIC_VECTOR(10 TO 0);
        DS :OUT STD_LOGIC_VECTOR(10 TO 0)
       );
END ADD1;
ARCHITECTURE a OF ADD1 IS
BEGIN 
PROCESS(B)
BEGIN
DS<=B+3;
END PROCESS;
END a;