📄 qpsk.rpt
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Total input pins required: 1
Total fast input logic cells required: 0
Total output pins required: 11
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 85
Total flipflops required: 49
Total product terms required: 251
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 61
Synthesized logic cells: 4/ 128 ( 3%)
Device-Specific Information: e:\vhdcx\qpsk.rpt
qpsk
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
83 - - INPUT G 0 0 0 0 0 0 0 CP
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\vhdcx\qpsk.rpt
qpsk
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
58 91 F FF + t 0 0 0 0 2 1 20 CD (|FP2:17|:16)
79 125 H OUTPUT t 0 0 0 0 0 0 0 CS
60 93 F FF + t 0 0 0 0 14 1 0 CW (|FP2:17|:30)
75 118 H FF t 6 0 1 0 7 0 0 N0 (|CUN1:2|:23)
74 117 H OUTPUT t 0 0 0 0 1 0 0 N1 (|CUN1:2|:22)
70 109 G OUTPUT t 0 0 0 0 1 0 0 N2 (|CUN1:2|:21)
69 107 G OUTPUT t 0 0 0 0 1 0 0 N3 (|CUN1:2|:20)
68 105 G OUTPUT t 0 0 0 0 1 0 0 N4 (|CUN1:2|:19)
64 99 G FF t 6 0 0 0 7 0 0 N5 (|CUN1:2|:18)
65 101 G FF t 7 2 0 0 7 0 0 N6 (|CUN1:2|:17)
61 94 F FF t 0 0 0 0 7 0 0 N7 (|CUN1:2|:16)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\vhdcx\qpsk.rpt
qpsk
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(77) 123 H SOFT t 0 0 0 0 8 0 3 |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|cout_node
- 119 H SOFT t 0 0 0 0 3 0 1 |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|gcp2
- 121 H SOFT t 0 0 0 0 4 0 2 |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|g4
- 114 H SOFT t 0 0 0 0 2 0 1 |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node1
(76) 120 H SOFT t 0 0 0 0 3 0 1 |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node2
- 124 H SOFT t 0 0 0 0 2 0 1 |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node3
(80) 126 H SOFT t 0 0 0 0 2 0 1 |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node4
- 127 H SOFT t 0 0 0 0 3 0 1 |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node5
(81) 128 H SOFT t 0 0 0 0 7 0 1 |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node6
- 122 H SOFT t 0 0 0 0 8 0 1 |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node7
(24) 46 C SOFT t 0 0 0 0 2 0 1 |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder1|result_node0
- 47 C SOFT t 0 0 0 0 3 0 1 |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder1|result_node1
(25) 45 C SOFT t 0 0 0 0 4 0 1 |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder1|result_node2
- 116 H DFFE s t r 7 2 0 0 7 1 0 |CUN1:2|N4~58~fit~in1 (|CUN1:2|:19)
- 66 E DFFE s t r 13 0 0 0 7 1 0 |CUN1:2|N3~58~fit~in1 (|CUN1:2|:20)
- 44 C DFFE s t r 11 2 0 0 7 1 0 |CUN1:2|N2~58~fit~in1 (|CUN1:2|:21)
(56) 86 F DFFE s t r 16 2 0 0 7 1 0 |CUN1:2|N1~58~fit~in1 (|CUN1:2|:22)
- 68 E SOFT t 0 0 0 0 4 0 1 |FP2:17|LPM_ADD_SUB:192|addcore:adder|addcore:adder0|result_node3
- 74 E SOFT t 0 0 0 0 5 0 1 |FP2:17|LPM_ADD_SUB:192|addcore:adder|addcore:adder0|result_node4
- 76 E SOFT t 0 0 0 0 6 0 1 |FP2:17|LPM_ADD_SUB:192|addcore:adder|addcore:adder0|result_node5
(45) 67 E SOFT t 0 0 0 0 7 0 1 |FP2:17|LPM_ADD_SUB:192|addcore:adder|addcore:adder0|result_node6
(51) 77 E SOFT t 0 0 0 0 8 0 1 |FP2:17|LPM_ADD_SUB:192|addcore:adder|addcore:adder0|result_node7
- 78 E SOFT t 0 0 0 0 9 0 1 |FP2:17|LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node0
- 79 E SOFT t 0 0 0 0 10 0 1 |FP2:17|LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node1
(52) 80 E SOFT t 0 0 0 0 11 0 1 |FP2:17|LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node2
(55) 85 F SOFT t 0 0 0 0 12 0 1 |FP2:17|LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node3
- 87 F SOFT t 0 0 0 0 13 0 1 |FP2:17|LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node4
(57) 88 F DFFE + t 0 0 0 0 14 1 11 |FP2:17|TEMP12 (|FP2:17|:6)
- 84 F DFFE + t 0 0 0 0 14 1 12 |FP2:17|TEMP11 (|FP2:17|:7)
(54) 83 F DFFE + t 0 0 0 0 14 1 13 |FP2:17|TEMP10 (|FP2:17|:8)
- 89 F DFFE + t 0 0 0 0 14 1 14 |FP2:17|TEMP9 (|FP2:17|:9)
- 90 F DFFE + t 0 0 0 0 14 1 15 |FP2:17|TEMP8 (|FP2:17|:10)
- 92 F DFFE + t 0 0 0 0 14 1 16 |FP2:17|TEMP7 (|FP2:17|:11)
- 95 F DFFE + t 0 0 0 0 14 1 17 |FP2:17|TEMP6 (|FP2:17|:12)
(62) 96 F DFFE + t 0 0 0 0 14 1 18 |FP2:17|TEMP5 (|FP2:17|:13)
- 81 F DFFE + t 0 0 0 0 14 1 19 |FP2:17|TEMP4 (|FP2:17|:14)
- 82 F DFFE + t 0 0 0 0 14 1 20 |FP2:17|TEMP3 (|FP2:17|:15)
(44) 65 E TFFE + t 0 0 0 0 1 6 51 |FP2:17|TEMP1 (|FP2:17|:17)
- 1 A TFFE + t 0 0 0 0 0 2 21 |FP2:17|TEMP0 (|FP2:17|:18)
(48) 72 E SOFT t 0 0 0 0 4 0 1 |PZ:4|LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node3
- 71 E SOFT t 0 0 0 0 5 0 1 |PZ:4|LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node4
(46) 69 E SOFT t 0 0 0 0 6 0 1 |PZ:4|LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node5
(35) 59 D SOFT t 0 0 0 0 7 0 1 |PZ:4|LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node6
- 54 D SOFT t 0 0 0 0 8 0 1 |PZ:4|LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node7
(39) 53 D SOFT t 0 0 0 0 9 0 1 |PZ:4|LPM_ADD_SUB:238|addcore:adder|addcore:adder1|result_node0
(36) 57 D SOFT t 0 0 0 0 10 0 1 |PZ:4|LPM_ADD_SUB:238|addcore:adder|addcore:adder1|result_node1
- 55 D SOFT t 0 0 0 0 11 0 1 |PZ:4|LPM_ADD_SUB:238|addcore:adder|addcore:adder1|result_node2
(40) 51 D DFFE t 0 0 0 0 12 0 11 |PZ:4|:2
- 63 D DFFE t 0 0 0 0 13 0 12 |PZ:4|QJ110 (|PZ:4|:10)
- 62 D DFFE t 0 0 0 0 13 0 13 |PZ:4|QJ19 (|PZ:4|:11)
(34) 61 D DFFE t 0 0 0 0 13 0 14 |PZ:4|QJ18 (|PZ:4|:12)
- 60 D DFFE t 0 0 0 0 13 0 15 |PZ:4|QJ17 (|PZ:4|:13)
- 58 D DFFE t 0 0 0 0 13 0 16 |PZ:4|QJ16 (|PZ:4|:14)
(41) 49 D DFFE t 0 0 0 0 13 0 17 |PZ:4|QJ15 (|PZ:4|:15)
- 50 D DFFE t 0 0 0 0 13 0 18 |PZ:4|QJ14 (|PZ:4|:16)
- 52 D DFFE t 0 0 0 0 13 0 19 |PZ:4|QJ13 (|PZ:4|:17)
- 70 E TFFE t 0 0 0 0 3 0 19 |PZ:4|QJ12 (|PZ:4|:18)
(49) 73 E TFFE t 0 0 0 0 2 0 20 |PZ:4|QJ11 (|PZ:4|:19)
(50) 75 E TFFE t 0 0 0 0 1 0 21 |PZ:4|QJ10 (|PZ:4|:20)
(33) 64 D TFFE t 0 0 0 0 13 0 2 |PZ:4|QJ21 (|PZ:4|:21)
(37) 56 D TFFE t 0 0 0 0 12 0 2 |PZ:4|QJ20 (|PZ:4|:22)
(27) 43 C DFFE t 0 0 0 0 3 0 1 |PZ:4|Q11 (|PZ:4|:31)
- 42 C DFFE t 0 0 0 0 2 0 2 |PZ:4|Q10 (|PZ:4|:32)
- 33 C DFFE t 0 0 0 0 4 4 5 |SUOCUNF:5|SAV10 (|SUOCUNF:5|:37)
- 34 C DFFE t 0 0 0 0 5 4 6 |SUOCUNF:5|SAV9 (|SUOCUNF:5|:38)
- 113 H DFFE t 0 0 0 0 3 4 7 |SUOCUNF:5|SAV8 (|SUOCUNF:5|:39)
(31) 35 C DFFE t 0 0 0 0 3 4 6 |SUOCUNF:5|SAV7 (|SUOCUNF:5|:40)
(30) 37 C DFFE t 0 0 0 0 3 4 7 |SUOCUNF:5|SAV6 (|SUOCUNF:5|:41)
- 39 C DFFE t 0 0 0 0 3 4 8 |SUOCUNF:5|SAV5 (|SUOCUNF:5|:42)
- 41 C DFFE t 0 0 0 0 3 0 5 |SUOCUNF:5|SAV4 (|SUOCUNF:5|:43)
(28) 40 C DFFE t 0 0 0 0 3 0 5 |SUOCUNF:5|SAV3 (|SUOCUNF:5|:44)
(29) 38 C DFFE t 0 0 0 0 3 0 6 |SUOCUNF:5|SAV2 (|SUOCUNF:5|:45)
- 36 C DFFE t 0 0 0 0 3 0 7 |SUOCUNF:5|SAV1 (|SUOCUNF:5|:46)
(73) 115 H DFFE t 0 0 0 0 3 0 8 |SUOCUNF:5|SAV0 (|SUOCUNF:5|:47)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\vhdcx\qpsk.rpt
qpsk
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+- LC1 |FP2:17|TEMP0
|
| Other LABs fed by signals
| that feed LAB 'A'
LC | | A B C D E F G H | Logic cells that feed LAB 'A':
Pin
83 -> - | - - - - - - - - | <-- CP
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\vhdcx\qpsk.rpt
qpsk
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+----------------------------- LC46 |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder1|result_node0
| +--------------------------- LC47 |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder1|result_node1
| | +------------------------- LC45 |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder1|result_node2
| | | +----------------------- LC44 |CUN1:2|N2~58~fit~in1
| | | | +--------------------- LC43 |PZ:4|Q11
| | | | | +------------------- LC42 |PZ:4|Q10
| | | | | | +----------------- LC33 |SUOCUNF:5|SAV10
| | | | | | | +--------------- LC34 |SUOCUNF:5|SAV9
| | | | | | | | +------------- LC35 |SUOCUNF:5|SAV7
| | | | | | | | | +----------- LC37 |SUOCUNF:5|SAV6
| | | | | | | | | | +--------- LC39 |SUOCUNF:5|SAV5
| | | | | | | | | | | +------- LC41 |SUOCUNF:5|SAV4
| | | | | | | | | | | | +----- LC40 |SUOCUNF:5|SAV3
| | | | | | | | | | | | | +--- LC38 |SUOCUNF:5|SAV2
| | | | | | | | | | | | | | +- LC36 |SUOCUNF:5|SAV1
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':
LC47 -> - - - - - - - * - - - - - - - | - - * - - - - - | <-- |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder1|result_node1
LC45 -> - - - - - - * - - - - - - - - | - - * - - - - - | <-- |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder1|result_node2
LC43 -> - - - - - - - * - - - - - - - | - - * - - - - - | <-- |PZ:4|Q11
LC42 -> - - - - - - * * - - - - - - - | - - * - - - - - | <-- |PZ:4|Q10
LC33 -> - - * * - - - - - - - - - - - | - - * - * * * * | <-- |SUOCUNF:5|SAV10
LC34 -> - * * * - - - - - - - - - - - | - - * - * * * * | <-- |SUOCUNF:5|SAV9
LC35 -> - - - * - - - - - - - - - - - | - - * - * * * * | <-- |SUOCUNF:5|SAV7
LC37 -> - - - * - - - - - - - - - - - | - - * - * * * * | <-- |SUOCUNF:5|SAV6
LC39 -> - - - * - - - - - - - - - - - | - - * - * * * * | <-- |SUOCUNF:5|SAV5
Pin
83 -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- CP
LC123-> * * * - - - - - - - - - - - - | - - * - - - - - | <-- |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|cout_node
LC114-> - - - - - - - - - - - - - - * | - - * - - - - - | <-- |ADD1:1|LPM_ADD_SUB:56|addcore:adder|addcore:adder0|result_node1
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