pianyi.vhd

基于vhdl的qpsk算法研究与性能测试

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY pianyi IS
   PORT(
        CP:IN STD_LOGIC;
        QO:OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
        );
END pianyi;
ARCHITECTURE aa1 OF pianyi IS

SIGNAL QN:STD_LOGIC_VECTOR(5 DOWNTO 0);
BEGIN
PROCESS(CP)
VARIABLE A:STD_LOGIC_VECTOR(7 DOWNTO 0):="10011100";
VARIABLE Q1:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
IF (CP'EVENT AND CP='1') THEN
Q1:=A(1)&A(0);
A:=A(1 DOWNTO 0)&A(7 DOWNTO 2);
END IF;
CASE Q1 IS
    WHEN "00"=>QN<="011000";
    WHEN "01"=>QN<="101000";
    WHEN "10"=>QN<="001000";
    WHEN OTHERS=>QN<="111000";
END CASE;
END PROCESS;
QO<=QN;
END aa1;