📄 pianzhi.rpt
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Device-Specific Information: e:\vhdcx\pianzhi.rpt
pianzhi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC18 LD
| +----------------------------- LC19 |LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node6
| | +--------------------------- LC20 |LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node7
| | | +------------------------- LC32 |LPM_ADD_SUB:238|addcore:adder|addcore:adder1|result_node0
| | | | +----------------------- LC30 |LPM_ADD_SUB:238|addcore:adder|addcore:adder1|result_node1
| | | | | +--------------------- LC31 |LPM_ADD_SUB:238|addcore:adder|addcore:adder1|result_node2
| | | | | | +------------------- LC29 QJ110
| | | | | | | +----------------- LC28 QJ19
| | | | | | | | +--------------- LC27 QJ18
| | | | | | | | | +------------- LC26 QJ17
| | | | | | | | | | +----------- LC25 QJ16
| | | | | | | | | | | +--------- LC17 QJ15
| | | | | | | | | | | | +------- LC22 QJ14
| | | | | | | | | | | | | +----- LC21 QJ13
| | | | | | | | | | | | | | +--- LC24 QJ21
| | | | | | | | | | | | | | | +- LC23 QJ20
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC19 -> - - - - - - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node6
LC20 -> - - - - - - - - - * - - - - - - | - * | <-- |LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node7
LC32 -> - - - - - - - - * - - - - - - - | - * | <-- |LPM_ADD_SUB:238|addcore:adder|addcore:adder1|result_node0
LC30 -> - - - - - - - * - - - - - - - - | - * | <-- |LPM_ADD_SUB:238|addcore:adder|addcore:adder1|result_node1
LC31 -> - - - - - - * - - - - - - - - - | - * | <-- |LPM_ADD_SUB:238|addcore:adder|addcore:adder1|result_node2
LC29 -> * - - - - * * * * * * * * * * * | - * | <-- QJ110
LC28 -> * - - - * * * * * * * * * * * * | - * | <-- QJ19
LC27 -> * - - * * * * * * * * * * * * * | - * | <-- QJ18
LC26 -> * - * * * * * * * * * * * * * * | - * | <-- QJ17
LC25 -> * * * * * * * * * * * * * * * * | - * | <-- QJ16
LC17 -> * * * * * * * * * * * * * * * * | * * | <-- QJ15
LC22 -> * * * * * * * * * * * * * * * * | * * | <-- QJ14
LC21 -> * * * * * * * * * * * * * * * * | * * | <-- QJ13
LC23 -> - - - - - - - - - - - - - - * * | * * | <-- QJ20
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- CLK
LC14 -> - - - - - - - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node3
LC13 -> - - - - - - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node4
LC12 -> - - - - - - - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node5
LC4 -> * * * * * * * * * * * * * * * * | * * | <-- QJ12
LC3 -> * * * * * * * * * * * * * * * * | * * | <-- QJ11
LC2 -> * * * * * * * * * * * * * * * * | * * | <-- QJ10
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\vhdcx\pianzhi.rpt
pianzhi
** EQUATIONS **
CLK : INPUT;
-- Node name is 'LD' = ':2'
-- Equation name is 'LD', type is output
LD = DFFE( _EQ001 $ VCC, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = QJ10 & QJ11 & QJ12 & QJ13 & !QJ14 & !QJ15 & QJ16 & QJ17 &
QJ18 & QJ19 & QJ110;
-- Node name is ':20' = 'QJ10'
-- Equation name is 'QJ10', location is LC002, type is buried.
QJ10 = TFFE( VCC, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is ':19' = 'QJ11'
-- Equation name is 'QJ11', location is LC003, type is buried.
QJ11 = TFFE( QJ10, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is ':18' = 'QJ12'
-- Equation name is 'QJ12', location is LC004, type is buried.
QJ12 = TFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = QJ10 & QJ11;
-- Node name is ':17' = 'QJ13'
-- Equation name is 'QJ13', location is LC021, type is buried.
QJ13 = DFFE( _EQ003 $ _LC014, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = _LC014 & QJ10 & QJ11 & QJ12 & QJ13 & !QJ14 & !QJ15 & QJ16 &
QJ17 & QJ18 & QJ19 & QJ110;
-- Node name is ':16' = 'QJ14'
-- Equation name is 'QJ14', location is LC022, type is buried.
QJ14 = DFFE( _EQ004 $ _LC013, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = _LC013 & QJ10 & QJ11 & QJ12 & QJ13 & !QJ14 & !QJ15 & QJ16 &
QJ17 & QJ18 & QJ19 & QJ110;
-- Node name is ':15' = 'QJ15'
-- Equation name is 'QJ15', location is LC017, type is buried.
QJ15 = DFFE( _EQ005 $ _LC012, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = _LC012 & QJ10 & QJ11 & QJ12 & QJ13 & !QJ14 & !QJ15 & QJ16 &
QJ17 & QJ18 & QJ19 & QJ110;
-- Node name is ':14' = 'QJ16'
-- Equation name is 'QJ16', location is LC025, type is buried.
QJ16 = DFFE( _EQ006 $ _LC019, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = _LC019 & QJ10 & QJ11 & QJ12 & QJ13 & !QJ14 & !QJ15 & QJ16 &
QJ17 & QJ18 & QJ19 & QJ110;
-- Node name is ':13' = 'QJ17'
-- Equation name is 'QJ17', location is LC026, type is buried.
QJ17 = DFFE( _EQ007 $ _LC020, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = _LC020 & QJ10 & QJ11 & QJ12 & QJ13 & !QJ14 & !QJ15 & QJ16 &
QJ17 & QJ18 & QJ19 & QJ110;
-- Node name is ':12' = 'QJ18'
-- Equation name is 'QJ18', location is LC027, type is buried.
QJ18 = DFFE( _EQ008 $ _LC032, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = _LC032 & QJ10 & QJ11 & QJ12 & QJ13 & !QJ14 & !QJ15 & QJ16 &
QJ17 & QJ18 & QJ19 & QJ110;
-- Node name is ':11' = 'QJ19'
-- Equation name is 'QJ19', location is LC028, type is buried.
QJ19 = DFFE( _EQ009 $ _LC030, GLOBAL( CLK), VCC, VCC, VCC);
_EQ009 = _LC030 & QJ10 & QJ11 & QJ12 & QJ13 & !QJ14 & !QJ15 & QJ16 &
QJ17 & QJ18 & QJ19 & QJ110;
-- Node name is ':22' = 'QJ20'
-- Equation name is 'QJ20', location is LC023, type is buried.
QJ20 = TFFE( _EQ010, GLOBAL( CLK), VCC, VCC, VCC);
_EQ010 = QJ10 & QJ11 & QJ12 & QJ13 & !QJ14 & !QJ15 & QJ16 & QJ17 &
QJ18 & QJ19 & QJ110;
-- Node name is ':21' = 'QJ21'
-- Equation name is 'QJ21', location is LC024, type is buried.
QJ21 = TFFE( _EQ011, GLOBAL( CLK), VCC, VCC, VCC);
_EQ011 = QJ10 & QJ11 & QJ12 & QJ13 & !QJ14 & !QJ15 & QJ16 & QJ17 &
QJ18 & QJ19 & QJ20 & QJ110;
-- Node name is ':10' = 'QJ110'
-- Equation name is 'QJ110', location is LC029, type is buried.
QJ110 = DFFE( _EQ012 $ _LC031, GLOBAL( CLK), VCC, VCC, VCC);
_EQ012 = _LC031 & QJ10 & QJ11 & QJ12 & QJ13 & !QJ14 & !QJ15 & QJ16 &
QJ17 & QJ18 & QJ19 & QJ110;
-- Node name is 'QO0'
-- Equation name is 'QO0', location is LC007, type is output.
QO0 = LCELL( VCC $ VCC);
-- Node name is 'QO1'
-- Equation name is 'QO1', location is LC009, type is output.
QO1 = LCELL( VCC $ VCC);
-- Node name is 'QO2'
-- Equation name is 'QO2', location is LC010, type is output.
QO2 = LCELL( VCC $ VCC);
-- Node name is 'QO3'
-- Equation name is 'QO3', location is LC006, type is output.
QO3 = LCELL( GND $ VCC);
-- Node name is 'QO4'
-- Equation name is 'QO4', location is LC005, type is output.
QO4 = LCELL(!QO5 $ Q11);
-- Node name is 'QO5' = 'Q10'
-- Equation name is 'QO5', location is LC001, type is output.
QO5 = DFFE(!QJ21 $ GND, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is ':31' = 'Q11'
-- Equation name is 'Q11', location is LC008, type is buried.
Q11 = DFFE(!QJ20 $ QJ21, GLOBAL( CLK), VCC, VCC, VCC);
-- Node name is '|LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC014', type is buried
_LC014 = LCELL( QJ13 $ _EQ013);
_EQ013 = QJ10 & QJ11 & QJ12;
-- Node name is '|LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC013', type is buried
_LC013 = LCELL( QJ14 $ _EQ014);
_EQ014 = QJ10 & QJ11 & QJ12 & QJ13;
-- Node name is '|LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC012', type is buried
_LC012 = LCELL( QJ15 $ _EQ015);
_EQ015 = QJ10 & QJ11 & QJ12 & QJ13 & QJ14;
-- Node name is '|LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC019', type is buried
_LC019 = LCELL( QJ16 $ _EQ016);
_EQ016 = QJ10 & QJ11 & QJ12 & QJ13 & QJ14 & QJ15;
-- Node name is '|LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried
_LC020 = LCELL( QJ17 $ _EQ017);
_EQ017 = QJ10 & QJ11 & QJ12 & QJ13 & QJ14 & QJ15 & QJ16;
-- Node name is '|LPM_ADD_SUB:238|addcore:adder|addcore:adder1|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC032', type is buried
_LC032 = LCELL( QJ18 $ _EQ018);
_EQ018 = QJ10 & QJ11 & QJ12 & QJ13 & QJ14 & QJ15 & QJ16 & QJ17;
-- Node name is '|LPM_ADD_SUB:238|addcore:adder|addcore:adder1|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried
_LC030 = LCELL( QJ19 $ _EQ019);
_EQ019 = QJ10 & QJ11 & QJ12 & QJ13 & QJ14 & QJ15 & QJ16 & QJ17 &
QJ18;
-- Node name is '|LPM_ADD_SUB:238|addcore:adder|addcore:adder1|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( QJ110 $ _EQ020);
_EQ020 = QJ10 & QJ11 & QJ12 & QJ13 & QJ14 & QJ15 & QJ16 & QJ17 &
QJ18 & QJ19;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\vhdcx\pianzhi.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,555K
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