📄 pianzhi.rpt
字号:
Project Information e:\vhdcx\pianzhi.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 10/30/2008 09:04:01
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
PIANZHI
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
pianzhi EPM7032LC44-6 1 7 0 29 0 90 %
User Pins: 1 7 0
Project Information e:\vhdcx\pianzhi.rpt
** PROJECT COMPILATION MESSAGES **
Warning: Primitive 'QO3' is stuck at VCC
Warning: Primitive 'QO2' is stuck at GND
Warning: Primitive 'QO1' is stuck at GND
Warning: Primitive 'QO0' is stuck at GND
Project Information e:\vhdcx\pianzhi.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'CLK' chosen for auto global Clock
Project Information e:\vhdcx\pianzhi.rpt
** FILE HIERARCHY **
|lpm_add_sub:168|
|lpm_add_sub:168|addcore:adder|
|lpm_add_sub:168|addcore:adder|addcore:adder0|
|lpm_add_sub:168|altshift:result_ext_latency_ffs|
|lpm_add_sub:168|altshift:carry_ext_latency_ffs|
|lpm_add_sub:168|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:238|
|lpm_add_sub:238|addcore:adder|
|lpm_add_sub:238|addcore:adder|addcore:adder1|
|lpm_add_sub:238|addcore:adder|addcore:adder0|
|lpm_add_sub:238|altshift:result_ext_latency_ffs|
|lpm_add_sub:238|altshift:carry_ext_latency_ffs|
|lpm_add_sub:238|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\vhdcx\pianzhi.rpt
pianzhi
***** Logic for device 'pianzhi' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Device-Specific Information: e:\vhdcx\pianzhi.rpt
pianzhi
** ERROR SUMMARY **
Info: Chip 'pianzhi' in device 'EPM7032LC44-6' has less than 10% of logic cells available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
R R R
E E E
S S S
E E E
R R R
V V Q V G G G C G V
E E O C N N N L N E L
D D 5 C D D D K D D D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
RESERVED | 7 39 | RESERVED
QO4 | 8 38 | RESERVED
QO3 | 9 37 | RESERVED
GND | 10 36 | RESERVED
QO0 | 11 35 | VCC
RESERVED | 12 EPM7032LC44-6 34 | RESERVED
QO1 | 13 33 | RESERVED
QO2 | 14 32 | RESERVED
VCC | 15 31 | RESERVED
RESERVED | 16 30 | GND
RESERVED | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R R R
E E E E N C E E E E E
S S S S D C S S S S S
E E E E E E E E E
R R R R R R R R R
V V V V V V V V V
E E E E E E E E E
D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\vhdcx\pianzhi.rpt
pianzhi
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 13/16( 81%) 6/16( 37%) 0/16( 0%) 10/36( 27%)
B: LC17 - LC32 16/16(100%) 1/16( 6%) 0/16( 0%) 20/36( 55%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 7/32 ( 21%)
Total logic cells used: 29/32 ( 90%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 29/32 ( 90%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 7.55
Total fan-in: 219
Total input pins required: 1
Total output pins required: 7
Total bidirectional pins required: 0
Total logic cells required: 29
Total flipflops required: 16
Total product terms required: 47
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: e:\vhdcx\pianzhi.rpt
pianzhi
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT G 0 0 0 0 0 0 0 CLK
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\vhdcx\pianzhi.rpt
pianzhi
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
40 18 B FF + t 0 0 0 0 11 0 0 LD
11 7 A OUTPUT t 0 0 0 0 0 0 0 QO0
13 9 A OUTPUT t 0 0 0 0 0 0 0 QO1
14 10 A OUTPUT t 0 0 0 0 0 0 0 QO2
9 6 A OUTPUT t 0 0 0 0 0 0 0 QO3
8 5 A OUTPUT t 0 0 0 0 2 0 0 QO4
4 1 A FF + t 0 0 0 0 1 1 0 QO5 (:32)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\vhdcx\pianzhi.rpt
pianzhi
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(19) 14 A SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node3
(18) 13 A SOFT t 0 0 0 0 5 0 1 |LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node4
(17) 12 A SOFT t 0 0 0 0 6 0 1 |LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node5
(39) 19 B SOFT t 0 0 0 0 7 0 1 |LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node6
(38) 20 B SOFT t 0 0 0 0 8 0 1 |LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node7
(24) 32 B SOFT t 0 0 0 0 9 0 1 |LPM_ADD_SUB:238|addcore:adder|addcore:adder1|result_node0
(26) 30 B SOFT t 0 0 0 0 10 0 1 |LPM_ADD_SUB:238|addcore:adder|addcore:adder1|result_node1
(25) 31 B SOFT t 0 0 0 0 11 0 1 |LPM_ADD_SUB:238|addcore:adder|addcore:adder1|result_node2
(27) 29 B DFFE + t 0 0 0 0 12 1 11 QJ110 (:10)
(28) 28 B DFFE + t 0 0 0 0 12 1 12 QJ19 (:11)
(29) 27 B DFFE + t 0 0 0 0 12 1 13 QJ18 (:12)
(31) 26 B DFFE + t 0 0 0 0 12 1 14 QJ17 (:13)
(32) 25 B DFFE + t 0 0 0 0 12 1 15 QJ16 (:14)
(41) 17 B DFFE + t 0 0 0 0 12 1 16 QJ15 (:15)
(36) 22 B DFFE + t 0 0 0 0 12 1 17 QJ14 (:16)
(37) 21 B DFFE + t 0 0 0 0 12 1 18 QJ13 (:17)
(7) 4 A TFFE + t 0 0 0 0 2 1 18 QJ12 (:18)
(6) 3 A TFFE + t 0 0 0 0 1 1 19 QJ11 (:19)
(5) 2 A TFFE + t 0 0 0 0 0 1 20 QJ10 (:20)
(33) 24 B TFFE + t 0 0 0 0 12 1 1 QJ21 (:21)
(34) 23 B TFFE + t 0 0 0 0 11 0 2 QJ20 (:22)
(12) 8 A DFFE + t 0 0 0 0 2 1 0 Q11 (:31)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\vhdcx\pianzhi.rpt
pianzhi
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------- LC14 |LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node3
| +----------------------- LC13 |LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node4
| | +--------------------- LC12 |LPM_ADD_SUB:238|addcore:adder|addcore:adder0|result_node5
| | | +------------------- LC7 QO0
| | | | +----------------- LC9 QO1
| | | | | +--------------- LC10 QO2
| | | | | | +------------- LC6 QO3
| | | | | | | +----------- LC5 QO4
| | | | | | | | +--------- LC1 QO5
| | | | | | | | | +------- LC4 QJ12
| | | | | | | | | | +----- LC3 QJ11
| | | | | | | | | | | +--- LC2 QJ10
| | | | | | | | | | | | +- LC8 Q11
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'A':
LC1 -> - - - - - - - * - - - - - | * - | <-- QO5
LC4 -> * * * - - - - - - * - - - | * * | <-- QJ12
LC3 -> * * * - - - - - - * * - - | * * | <-- QJ11
LC2 -> * * * - - - - - - * * * - | * * | <-- QJ10
LC8 -> - - - - - - - * - - - - - | * - | <-- Q11
Pin
43 -> - - - - - - - - - - - - - | - - | <-- CLK
LC17 -> - - * - - - - - - - - - - | * * | <-- QJ15
LC22 -> - * * - - - - - - - - - - | * * | <-- QJ14
LC21 -> * * * - - - - - - - - - - | * * | <-- QJ13
LC24 -> - - - - - - - - * - - - * | * - | <-- QJ21
LC23 -> - - - - - - - - - - - - * | * * | <-- QJ20
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -