📄 fp2.rpt
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Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC17 CW
| +----------------------------- LC31 |LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node0
| | +--------------------------- LC32 |LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node1
| | | +------------------------- LC19 |LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node2
| | | | +----------------------- LC20 |LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node3
| | | | | +--------------------- LC30 |LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node4
| | | | | | +------------------- LC29 TEMP12
| | | | | | | +----------------- LC28 TEMP11
| | | | | | | | +--------------- LC27 TEMP10
| | | | | | | | | +------------- LC26 TEMP9
| | | | | | | | | | +----------- LC25 TEMP8
| | | | | | | | | | | +--------- LC18 TEMP7
| | | | | | | | | | | | +------- LC21 TEMP6
| | | | | | | | | | | | | +----- LC22 TEMP5
| | | | | | | | | | | | | | +--- LC23 TEMP4
| | | | | | | | | | | | | | | +- LC24 TEMP3
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC17 -> * - - - - - - - - - - - - - - - | - * | <-- CW
LC31 -> - - - - - - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node0
LC32 -> - - - - - - - - - * - - - - - - | - * | <-- |LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node1
LC19 -> - - - - - - - - * - - - - - - - | - * | <-- |LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node2
LC20 -> - - - - - - - * - - - - - - - - | - * | <-- |LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node3
LC30 -> - - - - - - * - - - - - - - - - | - * | <-- |LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node4
LC29 -> * - - - - * * * * * * * * * * * | - * | <-- TEMP12
LC28 -> * - - - * * * * * * * * * * * * | - * | <-- TEMP11
LC27 -> * - - * * * * * * * * * * * * * | - * | <-- TEMP10
LC26 -> * - * * * * * * * * * * * * * * | - * | <-- TEMP9
LC25 -> * * * * * * * * * * * * * * * * | - * | <-- TEMP8
LC18 -> * * * * * * * * * * * * * * * * | * * | <-- TEMP7
LC21 -> * * * * * * * * * * * * * * * * | * * | <-- TEMP6
LC22 -> * * * * * * * * * * * * * * * * | * * | <-- TEMP5
LC23 -> * * * * * * * * * * * * * * * * | * * | <-- TEMP4
LC24 -> * * * * * * * * * * * * * * * * | * * | <-- TEMP3
Pin
43 -> - - - - - - - - - - - - - - - - | - - | <-- CP
LC1 -> * * * * * * * * * * * * * * * * | * * | <-- CD
LC2 -> * * * * * * * * * * * * * * * * | * * | <-- CLK
LC13 -> - - - - - - - - - - - - - - - * | - * | <-- |LPM_ADD_SUB:192|addcore:adder|addcore:adder0|result_node3
LC12 -> - - - - - - - - - - - - - - * - | - * | <-- |LPM_ADD_SUB:192|addcore:adder|addcore:adder0|result_node4
LC9 -> - - - - - - - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:192|addcore:adder|addcore:adder0|result_node5
LC8 -> - - - - - - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:192|addcore:adder|addcore:adder0|result_node6
LC4 -> - - - - - - - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:192|addcore:adder|addcore:adder0|result_node7
LC3 -> * * * * * * * * * * * * * * * * | * * | <-- TEMP0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\vhdcx\fp2.rpt
fp2
** EQUATIONS **
CP : INPUT;
-- Node name is 'CD' = 'TEMP2'
-- Equation name is 'CD', location is LC001, type is output.
CD = TFFE( _EQ001, GLOBAL( CP), VCC, VCC, VCC);
_EQ001 = CLK & TEMP0;
-- Node name is 'CLK' = 'TEMP1'
-- Equation name is 'CLK', location is LC002, type is output.
CLK = TFFE( TEMP0, GLOBAL( CP), VCC, VCC, VCC);
-- Node name is 'CS'
-- Equation name is 'CS', location is LC005, type is output.
CS = LCELL( GND $ GND);
-- Node name is 'CW' = 'TEM1'
-- Equation name is 'CW', location is LC017, type is output.
CW = DFFE( _EQ002 $ !CLK, GLOBAL( CP), VCC, VCC, VCC);
_EQ002 = CD & CLK & CW & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6 &
TEMP7 & TEMP8 & TEMP9 & TEMP10 & TEMP11 & TEMP12;
-- Node name is ':18' = 'TEMP0'
-- Equation name is 'TEMP0', location is LC003, type is buried.
TEMP0 = TFFE( VCC, GLOBAL( CP), VCC, VCC, VCC);
-- Node name is ':15' = 'TEMP3'
-- Equation name is 'TEMP3', location is LC024, type is buried.
TEMP3 = DFFE( _EQ003 $ _LC013, GLOBAL( CP), VCC, VCC, VCC);
_EQ003 = CD & CLK & _LC013 & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6 &
TEMP7 & TEMP8 & TEMP9 & TEMP10 & TEMP11 & TEMP12;
-- Node name is ':14' = 'TEMP4'
-- Equation name is 'TEMP4', location is LC023, type is buried.
TEMP4 = DFFE( _EQ004 $ _LC012, GLOBAL( CP), VCC, VCC, VCC);
_EQ004 = CD & CLK & _LC012 & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6 &
TEMP7 & TEMP8 & TEMP9 & TEMP10 & TEMP11 & TEMP12;
-- Node name is ':13' = 'TEMP5'
-- Equation name is 'TEMP5', location is LC022, type is buried.
TEMP5 = DFFE( _EQ005 $ _LC009, GLOBAL( CP), VCC, VCC, VCC);
_EQ005 = CD & CLK & _LC009 & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6 &
TEMP7 & TEMP8 & TEMP9 & TEMP10 & TEMP11 & TEMP12;
-- Node name is ':12' = 'TEMP6'
-- Equation name is 'TEMP6', location is LC021, type is buried.
TEMP6 = DFFE( _EQ006 $ _LC008, GLOBAL( CP), VCC, VCC, VCC);
_EQ006 = CD & CLK & _LC008 & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6 &
TEMP7 & TEMP8 & TEMP9 & TEMP10 & TEMP11 & TEMP12;
-- Node name is ':11' = 'TEMP7'
-- Equation name is 'TEMP7', location is LC018, type is buried.
TEMP7 = DFFE( _EQ007 $ _LC004, GLOBAL( CP), VCC, VCC, VCC);
_EQ007 = CD & CLK & _LC004 & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6 &
TEMP7 & TEMP8 & TEMP9 & TEMP10 & TEMP11 & TEMP12;
-- Node name is ':10' = 'TEMP8'
-- Equation name is 'TEMP8', location is LC025, type is buried.
TEMP8 = DFFE( _EQ008 $ _LC031, GLOBAL( CP), VCC, VCC, VCC);
_EQ008 = CD & CLK & _LC031 & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6 &
TEMP7 & TEMP8 & TEMP9 & TEMP10 & TEMP11 & TEMP12;
-- Node name is ':9' = 'TEMP9'
-- Equation name is 'TEMP9', location is LC026, type is buried.
TEMP9 = DFFE( _EQ009 $ _LC032, GLOBAL( CP), VCC, VCC, VCC);
_EQ009 = CD & CLK & _LC032 & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6 &
TEMP7 & TEMP8 & TEMP9 & TEMP10 & TEMP11 & TEMP12;
-- Node name is ':8' = 'TEMP10'
-- Equation name is 'TEMP10', location is LC027, type is buried.
TEMP10 = DFFE( _EQ010 $ _LC019, GLOBAL( CP), VCC, VCC, VCC);
_EQ010 = CD & CLK & _LC019 & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6 &
TEMP7 & TEMP8 & TEMP9 & TEMP10 & TEMP11 & TEMP12;
-- Node name is ':7' = 'TEMP11'
-- Equation name is 'TEMP11', location is LC028, type is buried.
TEMP11 = DFFE( _EQ011 $ _LC020, GLOBAL( CP), VCC, VCC, VCC);
_EQ011 = CD & CLK & _LC020 & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6 &
TEMP7 & TEMP8 & TEMP9 & TEMP10 & TEMP11 & TEMP12;
-- Node name is ':6' = 'TEMP12'
-- Equation name is 'TEMP12', location is LC029, type is buried.
TEMP12 = DFFE( _EQ012 $ _LC030, GLOBAL( CP), VCC, VCC, VCC);
_EQ012 = CD & CLK & _LC030 & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6 &
TEMP7 & TEMP8 & TEMP9 & TEMP10 & TEMP11 & TEMP12;
-- Node name is '|LPM_ADD_SUB:192|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC013', type is buried
_LC013 = LCELL( TEMP3 $ _EQ013);
_EQ013 = CD & CLK & TEMP0;
-- Node name is '|LPM_ADD_SUB:192|addcore:adder|addcore:adder0|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC012', type is buried
_LC012 = LCELL( TEMP4 $ _EQ014);
_EQ014 = CD & CLK & TEMP0 & TEMP3;
-- Node name is '|LPM_ADD_SUB:192|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC009', type is buried
_LC009 = LCELL( TEMP5 $ _EQ015);
_EQ015 = CD & CLK & TEMP0 & TEMP3 & TEMP4;
-- Node name is '|LPM_ADD_SUB:192|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC008', type is buried
_LC008 = LCELL( TEMP6 $ _EQ016);
_EQ016 = CD & CLK & TEMP0 & TEMP3 & TEMP4 & TEMP5;
-- Node name is '|LPM_ADD_SUB:192|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC004', type is buried
_LC004 = LCELL( TEMP7 $ _EQ017);
_EQ017 = CD & CLK & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6;
-- Node name is '|LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node0' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( TEMP8 $ _EQ018);
_EQ018 = CD & CLK & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6 & TEMP7;
-- Node name is '|LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC032', type is buried
_LC032 = LCELL( TEMP9 $ _EQ019);
_EQ019 = CD & CLK & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6 & TEMP7 &
TEMP8;
-- Node name is '|LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC019', type is buried
_LC019 = LCELL( TEMP10 $ _EQ020);
_EQ020 = CD & CLK & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6 & TEMP7 &
TEMP8 & TEMP9;
-- Node name is '|LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC020', type is buried
_LC020 = LCELL( TEMP11 $ _EQ021);
_EQ021 = CD & CLK & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6 & TEMP7 &
TEMP8 & TEMP9 & TEMP10;
-- Node name is '|LPM_ADD_SUB:192|addcore:adder|addcore:adder1|result_node4' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried
_LC030 = LCELL( TEMP12 $ _EQ022);
_EQ022 = CD & CLK & TEMP0 & TEMP3 & TEMP4 & TEMP5 & TEMP6 & TEMP7 &
TEMP8 & TEMP9 & TEMP10 & TEMP11;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\vhdcx\fp2.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 21,102K
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