pz.vhd

基于vhdl的qpsk算法研究与性能测试

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY pz IS
   PORT(
        CLK:IN STD_LOGIC;
        LD:OUT STD_LOGIC;
        QO:OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
        );
END pz;
ARCHITECTURE aa1 OF pz IS
SIGNAL QJ1:STD_LOGIC_VECTOR(10 DOWNTO 0):="00000000000";
SIGNAL QJ2:STD_LOGIC_VECTOR(1 DOWNTO 0):="00";
SIGNAL Q1:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL QN:STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL IN1:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IN1<="10000111";
PROCESS(CLK)
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
    IF(QJ1="11111001111") THEN
      QJ1<="00000000000";
      LD<='0';
      IF (QJ2="11") THEN
      QJ2<="00";
      ELSE 
      QJ2<=QJ2+1;
      END IF;
    ELSE  
      QJ1<=QJ1+1;
      LD<='1';
    END IF;
CASE QJ2 IS
    WHEN "00"=>Q1<=IN1(1 DOWNTO 0);
    WHEN "01"=>Q1<=IN1(3 DOWNTO 2);
    WHEN "10"=>Q1<=IN1(5 DOWNTO 4);
    WHEN  OTHERS=>Q1<=IN1(7 DOWNTO 6);
END CASE;
END IF;
CASE Q1 IS
    WHEN "00"=>QN<="011000";
    WHEN "01"=>QN<="101000";
    WHEN "10"=>QN<="001000";
    WHEN OTHERS=>QN<="111000";
END CASE;
END PROCESS;
QO<=QN;
END aa1;