ddc.xml

vhdl硬件设计实现一个数字上变频器

<interfaceDefinition version='1.1' language='vhdl' kind='component' name='ddc'>
  <useClause path='ieee.std_logic_arith.all' />
  <useClause path='ieee.std_logic_1164.all' />
    <portList>

      <port name='clk' direction='in' type='std_logic' />
      <port name='ddc_ena' direction='in' type='std_logic' />
      <port name='reset' direction='in' type='std_logic' />
      <port name='datin' direction='in' type='std_logic_vector (15 downto 0)' />
      <port name='i_out' direction='out' type='std_logic_vector (15 downto 0)' />
      <port name='q_out' direction='out' type='std_logic_vector (15 downto 0)' />
      <port name='cout' direction='out' type='std_logic_vector (1 downto 0)' />

    </portList>
</interfaceDefinition>