ddc_tb.vhd.bak

来自「vhdl硬件设计实现一个数字上变频器」· BAK 代码 · 共 38 行

LIBRARY ieee  ; 
LIBRARY ieee  ; 
USE ieee.std_logic_arith.all  ; 
USE ieee.std_logic_1164.all  ; 
ENTITY ddc_tb  IS 
END ; 
 
ARCHITECTURE ddc_tb_arch OF ddc_tb IS
  SIGNAL q_out   :  std_logic_vector (15 downto 0)  ; 
  SIGNAL i_out   :  std_logic_vector (15 downto 0)  ; 
  SIGNAL datin   :  std_logic_vector (15 downto 0)  ; 
  SIGNAL ddc_ena   :  std_logic  ; 
  SIGNAL clk   :  std_logic  ; 
  SIGNAL cout   :  std_logic_vector (1 downto 0)  ; 
  SIGNAL reset   :  std_logic  ; 
  COMPONENT ddc  
    PORT ( 
      q_out  : out std_logic_vector (15 downto 0) ; 
      i_out  : out std_logic_vector (15 downto 0) ; 
      datin  : in std_logic_vector (15 downto 0) ; 
      ddc_ena  : in std_logic ; 
      clk  : in std_logic ; 
      cout  : out std_logic_vector (1 downto 0) ; 
      reset  : in std_logic ); 
  END COMPONENT ; 
BEGIN
  DUT  : ddc  
    PORT MAP ( 
      q_out   => q_out  ,
      i_out   => i_out  ,
      datin   => datin  ,
      ddc_ena   => ddc_ena  ,
      clk   => clk  ,
      cout   => cout  ,
      reset   => reset   ) ; 
END ;