freque4.vhd

基于bpsk的vhdl语言编程与性能仿真

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity freque4 is
port(
      clk:in std_logic;
      flck:out std_logic
       );
end freque4;
architecture a of freque4 is
signal temp:std_logic_vector(1 downto 0);
begin
   process(clk)
   begin
   if(clk'event and clk='1')then
   if temp="11" then
      temp<="00";
   else temp<=temp+1;
   end if;
   end if;
   flck<=temp(1);
end process;
end a;