ad.vhd

基于bpsk的vhdl语言编程与性能仿真

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ad is
port(
      clk:in std_logic;
      da_cs,da_wr,da_spab:out std_logic
       );
end ad;
architecture d of ad is
signal temp:std_logic_vector(1 downto 0);
begin
   process(clk)
   begin
   if(clk'event and clk='1')then
   if temp="11" then
      temp<="00";
   else temp<=temp+1;
   end if;
   end if;
   case temp is
     when "00"=>da_cs<='0';da_wr<='1';da_spab<='0';
     when "01"=>da_cs<='0';da_wr<='0';da_spab<='0'; 
     when "10"=>da_cs<='0';da_wr<='1';da_spab<='0';
     when others=>da_cs<='1';da_wr<='1';da_spab<='1';
    end case;
    end process;
end d;