📄 address.rpt
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| | | | | +--------------------- LC21 ass5
| | | | | | +------------------- LC31 |LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node5
| | | | | | | +----------------- LC30 |LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node6
| | | | | | | | +--------------- LC29 |LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node7
| | | | | | | | | +------------- LC23 |LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node5
| | | | | | | | | | +----------- LC24 |LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node6
| | | | | | | | | | | +--------- LC25 |LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node7
| | | | | | | | | | | | +------- LC26 temp3
| | | | | | | | | | | | | +----- LC27 temp2
| | | | | | | | | | | | | | +--- LC28 temp1
| | | | | | | | | | | | | | | +- LC32 temp0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC17 -> * * * * * * * * * * * * * - * * | - * | <-- ass0
LC18 -> * * * * * * * * * * * * * - * * | - * | <-- ass1
LC19 -> * * * * * * - * * - * * * - * * | - * | <-- ass2
LC20 -> * * * * * * - - * - - * * - * * | - * | <-- ass3
LC22 -> * * * * * * - - - - - - * - * * | - * | <-- ass4
LC21 -> * * * * * * - - - - - - * - * * | - * | <-- ass5
LC31 -> - * - - - - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node5
LC30 -> - - * - - - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node6
LC29 -> - - - * - - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node7
LC23 -> - * - - - - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node5
LC24 -> - - * - - - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node6
LC25 -> - - - * - - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node7
LC26 -> * * * * * * * * * * * * * - * * | - * | <-- temp3
LC27 -> * * * * * * * * * * * * * * * * | - * | <-- temp2
LC28 -> * * * * * * * * * - - - * * * * | - * | <-- temp1
LC32 -> * * * * * * * * * - - - * * * * | - * | <-- temp0
Pin
4 -> * * * * * * - - - - - - * * * * | - * | <-- d
43 -> - - - - - - - - - - - - - - - - | - - | <-- fclk
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\bfsk\address.rpt
address
** EQUATIONS **
d : INPUT;
fclk : INPUT;
-- Node name is 'ass0' = 'temp4'
-- Equation name is 'ass0', location is LC017, type is output.
ass0 = TFFE( _EQ001, GLOBAL( fclk), VCC, VCC, VCC);
_EQ001 = ass0 & ass1 & ass2 & ass3 & ass4 & ass5 & temp0 & temp1 &
temp2 & temp3
# !d & temp0 & temp1 & temp2 & temp3
# d & temp2 & temp3;
-- Node name is 'ass1' = 'temp5'
-- Equation name is 'ass1', location is LC018, type is output.
ass1 = DFFE( _EQ002 $ VCC, GLOBAL( fclk), VCC, VCC, VCC);
_EQ002 = ass0 & ass1 & ass2 & ass3 & ass4 & ass5 & temp0 & temp1 &
temp2 & temp3
# d & !_LC023
# !d & !_LC031;
-- Node name is 'ass2' = 'temp6'
-- Equation name is 'ass2', location is LC019, type is output.
ass2 = DFFE( _EQ003 $ VCC, GLOBAL( fclk), VCC, VCC, VCC);
_EQ003 = ass0 & ass1 & ass2 & ass3 & ass4 & ass5 & temp0 & temp1 &
temp2 & temp3
# d & !_LC024
# !d & !_LC030;
-- Node name is 'ass3' = 'temp7'
-- Equation name is 'ass3', location is LC020, type is output.
ass3 = DFFE( _EQ004 $ VCC, GLOBAL( fclk), VCC, VCC, VCC);
_EQ004 = ass0 & ass1 & ass2 & ass3 & ass4 & ass5 & temp0 & temp1 &
temp2 & temp3
# d & !_LC025
# !d & !_LC029;
-- Node name is 'ass4' = 'temp8'
-- Equation name is 'ass4', location is LC022, type is output.
ass4 = TFFE( _EQ005, GLOBAL( fclk), VCC, VCC, VCC);
_EQ005 = ass0 & ass1 & ass2 & ass3 & ass4 & ass5 & temp0 & temp1 &
temp2 & temp3
# ass0 & ass1 & ass2 & ass3 & !d & temp0 & temp1 & temp2 &
temp3
# ass0 & ass1 & ass2 & ass3 & d & temp2 & temp3;
-- Node name is 'ass5' = 'temp9'
-- Equation name is 'ass5', location is LC021, type is output.
ass5 = TFFE( _EQ006, GLOBAL( fclk), VCC, VCC, VCC);
_EQ006 = ass0 & ass1 & ass2 & ass3 & ass4 & ass5 & temp0 & temp1 &
temp2 & temp3
# ass0 & ass1 & ass2 & ass3 & ass4 & !d & temp0 & temp1 &
temp2 & temp3
# ass0 & ass1 & ass2 & ass3 & ass4 & d & temp2 & temp3;
-- Node name is ':18' = 'temp0'
-- Equation name is 'temp0', location is LC032, type is buried.
temp0 = TFFE( _EQ007, GLOBAL( fclk), VCC, VCC, VCC);
_EQ007 = ass0 & ass1 & ass2 & ass3 & ass4 & ass5 & temp0 & temp1 &
temp2 & temp3
# !d;
-- Node name is ':17' = 'temp1'
-- Equation name is 'temp1', location is LC028, type is buried.
temp1 = TFFE( _EQ008, GLOBAL( fclk), VCC, VCC, VCC);
_EQ008 = ass0 & ass1 & ass2 & ass3 & ass4 & ass5 & temp0 & temp1 &
temp2 & temp3
# !d & temp0;
-- Node name is ':16' = 'temp2'
-- Equation name is 'temp2', location is LC027, type is buried.
temp2 = TFFE( _EQ009, GLOBAL( fclk), VCC, VCC, VCC);
_EQ009 = temp0 & temp1
# d;
-- Node name is ':15' = 'temp3'
-- Equation name is 'temp3', location is LC026, type is buried.
temp3 = TFFE( _EQ010, GLOBAL( fclk), VCC, VCC, VCC);
_EQ010 = ass0 & ass1 & ass2 & ass3 & ass4 & ass5 & temp0 & temp1 &
temp2 & temp3
# !d & temp0 & temp1 & temp2
# d & temp2;
-- Node name is '|LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC031', type is buried
_LC031 = LCELL( ass1 $ _EQ011);
_EQ011 = ass0 & temp0 & temp1 & temp2 & temp3;
-- Node name is '|LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried
_LC030 = LCELL( ass2 $ _EQ012);
_EQ012 = ass0 & ass1 & temp0 & temp1 & temp2 & temp3;
-- Node name is '|LPM_ADD_SUB:135|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried
_LC029 = LCELL( ass3 $ _EQ013);
_EQ013 = ass0 & ass1 & ass2 & temp0 & temp1 & temp2 & temp3;
-- Node name is '|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node5' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried
_LC023 = LCELL( ass1 $ _EQ014);
_EQ014 = ass0 & temp2 & temp3;
-- Node name is '|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node6' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried
_LC024 = LCELL( ass2 $ _EQ015);
_EQ015 = ass0 & ass1 & temp2 & temp3;
-- Node name is '|LPM_ADD_SUB:186|addcore:adder|addcore:adder0|result_node7' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( ass3 $ _EQ016);
_EQ016 = ass0 & ass1 & ass2 & temp2 & temp3;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\bfsk\address.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,066K
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