📄 store.rpt
字号:
ass1 : INPUT;
ass2 : INPUT;
ass3 : INPUT;
ass4 : INPUT;
ass5 : INPUT;
-- Node name is 'd0'
-- Equation name is 'd0', location is LC007, type is output.
d0 = LCELL( _EQ001 $ _EQ002);
_EQ001 = !ass1 & ass2 & !ass3 & !ass4 & ass5 & !_LC031 & !_LC032
# !ass0 & ass2 & !ass3 & !ass4 & !ass5 & !_LC031 & !_LC032
# ass0 & ass1 & ass2 & !ass5 & !_LC031 & !_LC032
# ass0 & !ass1 & ass4 & ass5 & !_LC031 & !_LC032;
_EQ002 = !_LC031 & !_LC032;
-- Node name is 'd1'
-- Equation name is 'd1', location is LC028, type is output.
d1 = LCELL( _EQ003 $ _EQ004);
_EQ003 = ass0 & !ass1 & ass3 & ass4 & !ass5
# ass2 & ass3 & !ass5 & _X001
# !ass1 & ass2 & !ass5 & _X001;
_X001 = EXP( ass0 & !ass4);
_EQ004 = !_LC029 & !_LC030 & _X002 & _X003 & _X004 & _X005;
_X002 = EXP( ass0 & ass1 & ass2 & !ass3 & ass5);
_X003 = EXP(!ass0 & !ass2 & ass4 & ass5);
_X004 = EXP( ass0 & !ass2 & !ass3 & !ass4 & !ass5);
_X005 = EXP(!ass2 & !ass3 & ass4 & ass5);
-- Node name is 'd2'
-- Equation name is 'd2', location is LC010, type is output.
d2 = LCELL( _EQ005 $ _EQ006);
_EQ005 = ass0 & ass1 & !ass3 & ass4 & !ass5 & !_LC024 & !_LC025 & _X005
# ass0 & !ass1 & ass2 & ass3 & !ass4 & !_LC024 & !_LC025 & _X005
# !ass0 & ass1 & ass2 & ass4 & !ass5 & !_LC024 & !_LC025 & _X005
# ass1 & ass2 & !ass3 & !ass4 & ass5 & !_LC024 & !_LC025 & _X005;
_X005 = EXP(!ass2 & !ass3 & ass4 & ass5);
_EQ006 = !_LC024 & !_LC025 & _X005;
_X005 = EXP(!ass2 & !ass3 & ass4 & ass5);
-- Node name is 'd3'
-- Equation name is 'd3', location is LC011, type is output.
d3 = LCELL( _EQ007 $ _EQ008);
_EQ007 = !ass0 & ass1 & !ass2 & ass3 & ass4 & !ass5 & !_LC022 & !_LC023 &
_X005
# ass0 & !ass1 & ass3 & ass4 & !ass5 & !_LC022 & !_LC023 & _X005
# ass0 & ass2 & !ass3 & ass4 & !ass5 & !_LC022 & !_LC023 & _X005
# !ass0 & !ass1 & !ass2 & ass4 & ass5 & !_LC022 & !_LC023 & _X005;
_X005 = EXP(!ass2 & !ass3 & ass4 & ass5);
_EQ008 = !_LC022 & !_LC023 & _X005;
_X005 = EXP(!ass2 & !ass3 & ass4 & ass5);
-- Node name is 'd4'
-- Equation name is 'd4', location is LC009, type is output.
d4 = LCELL( _EQ009 $ ass5);
_EQ009 = !_LC020 & !_LC021 & _X002 & _X004;
_X002 = EXP( ass0 & ass1 & ass2 & !ass3 & ass5);
_X004 = EXP( ass0 & !ass2 & !ass3 & !ass4 & !ass5);
-- Node name is 'd5'
-- Equation name is 'd5', location is LC008, type is output.
d5 = LCELL( _EQ010 $ !ass5);
_EQ010 = !_LC018 & !_LC019;
-- Node name is 'd6'
-- Equation name is 'd6', location is LC027, type is output.
d6 = LCELL( _EQ011 $ _EQ012);
_EQ011 = ass0 & ass1 & ass2 & !ass4 & ass5 & !_LC017 & _X003 & _X006
# ass0 & ass1 & ass3 & ass4 & !ass5 & !_LC017 & _X003 & _X006
# ass1 & !ass2 & !ass3 & !ass4 & !ass5 & !_LC017 & _X003 & _X006
# ass0 & !ass2 & !ass3 & !ass4 & !ass5 & !_LC017 & _X003 & _X006;
_X003 = EXP(!ass0 & !ass2 & ass4 & ass5);
_X006 = EXP(!ass3 & ass4 & ass5);
_EQ012 = !_LC017 & _X003 & _X006;
_X003 = EXP(!ass0 & !ass2 & ass4 & ass5);
_X006 = EXP(!ass3 & ass4 & ass5);
-- Node name is 'd7'
-- Equation name is 'd7', location is LC026, type is output.
d7 = LCELL( _EQ013 $ !ass5);
_EQ013 = !ass0 & !ass1 & !ass2 & !ass3 & !ass4 & ass5
# !ass0 & !ass1 & !ass2 & !ass3 & !ass5;
-- Node name is '~2728~1'
-- Equation name is '~2728~1', location is LC017, type is buried.
-- synthesized logic cell
_LC017 = LCELL( _EQ014 $ GND);
_EQ014 = !ass1 & ass2 & !ass3 & !ass4 & !ass5
# ass2 & ass3 & ass4 & !ass5
# !ass1 & !ass2 & ass4 & ass5
# !ass0 & !ass1 & !ass2 & ass5
# ass3 & !ass4 & ass5;
-- Node name is '~2917~1'
-- Equation name is '~2917~1', location is LC018, type is buried.
-- synthesized logic cell
_LC018 = LCELL( _EQ015 $ GND);
_EQ015 = ass0 & !ass1 & !ass2 & ass3 & !ass4 & !ass5
# ass0 & ass1 & !ass2 & ass3 & ass5
# ass0 & ass1 & !ass2 & !ass5
# !ass0 & ass2 & !ass3 & ass5
# ass1 & ass3 & !ass4;
-- Node name is '~2917~2'
-- Equation name is '~2917~2', location is LC019, type is buried.
-- synthesized logic cell
_LC019 = LCELL( _EQ016 $ GND);
_EQ016 = !ass0 & !ass1 & !ass3
# !ass1 & ass2
# !ass3 & ass4;
-- Node name is '~3106~1'
-- Equation name is '~3106~1', location is LC020, type is buried.
-- synthesized logic cell
_LC020 = LCELL( _EQ017 $ GND);
_EQ017 = ass0 & ass1 & !ass2 & ass3 & !ass4 & ass5
# ass0 & !ass1 & !ass2 & !ass3 & !ass4 & ass5
# !ass0 & !ass1 & ass2 & !ass3 & !ass4 & ass5
# !ass0 & ass1 & !ass2 & !ass3 & !ass4 & ass5
# ass1 & ass2 & !ass3 & ass4 & ass5;
-- Node name is '~3106~2'
-- Equation name is '~3106~2', location is LC021, type is buried.
-- synthesized logic cell
_LC021 = LCELL( _EQ018 $ GND);
_EQ018 = ass0 & ass1 & ass2 & ass4 & !ass5
# !ass0 & ass1 & ass2 & !ass3 & !ass5
# ass0 & !ass1 & !ass2 & !ass4 & !ass5
# ass0 & ass2 & ass3 & ass4
# !ass0 & ass1 & !ass2 & ass3;
-- Node name is '~3295~1'
-- Equation name is '~3295~1', location is LC022, type is buried.
-- synthesized logic cell
_LC022 = LCELL( _EQ019 $ GND);
_EQ019 = ass1 & ass2 & !ass3 & !ass4 & !ass5
# ass0 & ass1 & !ass3 & !ass4 & !ass5
# ass0 & ass1 & ass3 & ass5
# !ass0 & ass1 & ass2 & ass5
# ass1 & !ass2 & !ass3 & ass5;
-- Node name is '~3295~2'
-- Equation name is '~3295~2', location is LC023, type is buried.
-- synthesized logic cell
_LC023 = LCELL( _EQ020 $ GND);
_EQ020 = !ass1 & ass2 & ass4 & !ass5
# ass0 & !ass2 & ass3 & !ass4
# !ass0 & !ass1 & !ass3 & ass4
# !ass0 & !ass1 & ass2 & !ass5;
-- Node name is '~3484~1'
-- Equation name is '~3484~1', location is LC024, type is buried.
-- synthesized logic cell
_LC024 = LCELL( _EQ021 $ GND);
_EQ021 = !ass0 & ass2 & ass3 & ass4 & !ass5
# !ass0 & ass1 & !ass2 & !ass3 & ass5
# !ass0 & !ass1 & ass2 & !ass3 & !ass4
# !ass0 & !ass1 & !ass2 & !ass3 & ass4
# !ass0 & ass1 & !ass2 & !ass4 & !ass5;
-- Node name is '~3484~2'
-- Equation name is '~3484~2', location is LC025, type is buried.
-- synthesized logic cell
_LC025 = LCELL( _EQ022 $ GND);
_EQ022 = ass0 & ass2 & ass3 & ass5
# ass1 & !ass2 & ass4 & ass5
# ass0 & ass2 & !ass3 & !ass5
# ass0 & !ass2 & ass3 & !ass5
# !ass1 & !ass2 & ass3 & !ass5;
-- Node name is '~3673~1'
-- Equation name is '~3673~1', location is LC029, type is buried.
-- synthesized logic cell
_LC029 = LCELL( _EQ023 $ GND);
_EQ023 = ass0 & ass1 & ass2 & !ass3 & !ass4
# ass0 & !ass1 & ass2 & ass3 & !ass4
# !ass0 & !ass1 & !ass2 & !ass3 & ass5
# ass1 & ass3 & !ass4 & ass5
# ass0 & ass3 & !ass4 & ass5;
-- Node name is '~3673~2'
-- Equation name is '~3673~2', location is LC030, type is buried.
-- synthesized logic cell
_LC030 = LCELL( _EQ024 $ GND);
_EQ024 = ass1 & !ass2 & !ass3 & ass4
# !ass0 & ass1 & !ass3 & ass4
# !ass0 & !ass3 & ass4 & ass5
# ass1 & !ass2 & !ass4 & !ass5;
-- Node name is '~3862~1'
-- Equation name is '~3862~1', location is LC031, type is buried.
-- synthesized logic cell
_LC031 = LCELL( _EQ025 $ GND);
_EQ025 = ass0 & ass1 & ass2 & !ass3
# !ass0 & !ass1 & ass3 & ass5
# ass0 & !ass2 & !ass4 & !ass5
# ass1 & !ass2 & !ass3 & !ass4
# !ass0 & !ass1 & !ass2 & ass4;
-- Node name is '~3862~2'
-- Equation name is '~3862~2', location is LC032, type is buried.
-- synthesized logic cell
_LC032 = LCELL( _EQ026 $ GND);
_EQ026 = ass0 & ass2 & ass4
# !ass0 & ass3 & ass4
# !ass1 & !ass2 & ass3
# !ass0 & !ass2 & ass5;
-- Shareable expanders that are duplicated in multiple LABs:
-- _X002 occurs in LABs A, B
-- _X004 occurs in LABs A, B
-- _X005 occurs in LABs A, B
Project Information e:\bfsk\store.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,067K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -