📄 store.rpt
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Project Information e:\bfsk\store.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 10/30/2008 08:33:59
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
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under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
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the intellectual property, including patents, copyrights, trademarks,
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***** Project compilation was successful
STORE
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
store EPM7032LC44-6 6 8 0 21 9 65 %
User Pins: 6 8 0
Device-Specific Information: e:\bfsk\store.rpt
store
***** Logic for device 'store' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
R R
E E
S S
E E
a a a R R
s s s V G G G G G V V
s s s C N N N N N E E
4 5 0 C D D D D D D D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
ass3 | 7 39 | RESERVED
ass2 | 8 38 | RESERVED
ass1 | 9 37 | RESERVED
GND | 10 36 | RESERVED
d0 | 11 35 | VCC
d5 | 12 EPM7032LC44-6 34 | RESERVED
d4 | 13 33 | RESERVED
d2 | 14 32 | RESERVED
VCC | 15 31 | d7
d3 | 16 30 | GND
RESERVED | 17 29 | d6
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R R d
E E E E N C E E E E 1
S S S S D C S S S S
E E E E E E E E
R R R R R R R R
V V V V V V V V
E E E E E E E E
D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\bfsk\store.rpt
store
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 5/16( 31%) 11/16( 68%) 6/16( 37%) 16/36( 44%)
B: LC17 - LC32 16/16(100%) 3/16( 18%) 16/16(100%) 9/36( 25%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 14/32 ( 43%)
Total logic cells used: 21/32 ( 65%)
Total shareable expanders used: 9/32 ( 28%)
Total Turbo logic cells used: 21/32 ( 65%)
Total shareable expanders not available (n/a): 13/32 ( 40%)
Average fan-in: 6.33
Total fan-in: 133
Total input pins required: 6
Total output pins required: 8
Total bidirectional pins required: 0
Total logic cells required: 21
Total flipflops required: 0
Total product terms required: 100
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 6
Synthesized logic cells: 13/ 32 ( 40%)
Device-Specific Information: e:\bfsk\store.rpt
store
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 7 13 ass0
9 (6) (A) INPUT 0 0 0 0 0 7 13 ass1
8 (5) (A) INPUT 0 0 0 0 0 7 13 ass2
7 (4) (A) INPUT 0 0 0 0 0 7 13 ass3
6 (3) (A) INPUT 0 0 0 0 0 7 13 ass4
5 (2) (A) INPUT 0 0 0 0 0 8 12 ass5
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\bfsk\store.rpt
store
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
11 7 A OUTPUT t 1 0 1 6 2 0 0 d0
28 28 B OUTPUT t 5 4 0 6 2 0 0 d1
14 10 A OUTPUT t 2 1 1 6 2 0 0 d2
16 11 A OUTPUT t 2 1 1 6 2 0 0 d3
13 9 A OUTPUT t 2 2 0 6 2 0 0 d4
12 8 A OUTPUT t 0 0 0 1 2 0 0 d5
29 27 B OUTPUT t 3 1 1 6 1 0 0 d6
31 26 B OUTPUT t 0 0 0 6 0 0 0 d7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\bfsk\store.rpt
store
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(41) 17 B SOFT s t 1 0 1 6 0 1 0 ~2728~1
(40) 18 B SOFT s t 1 0 1 6 0 1 0 ~2917~1
(39) 19 B SOFT s t 0 0 0 5 0 1 0 ~2917~2
(38) 20 B SOFT s t 1 0 1 6 0 1 0 ~3106~1
(37) 21 B SOFT s t 1 0 1 6 0 1 0 ~3106~2
(36) 22 B SOFT s t 1 0 1 6 0 1 0 ~3295~1
(34) 23 B SOFT s t 0 0 0 6 0 1 0 ~3295~2
(33) 24 B SOFT s t 1 0 1 6 0 1 0 ~3484~1
(32) 25 B SOFT s t 1 0 1 6 0 1 0 ~3484~2
(27) 29 B SOFT s t 1 0 1 6 0 1 0 ~3673~1
(26) 30 B SOFT s t 0 0 0 6 0 1 0 ~3673~2
(25) 31 B SOFT s t 1 0 1 6 0 1 0 ~3862~1
(24) 32 B SOFT s t 0 0 0 6 0 1 0 ~3862~2
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\bfsk\store.rpt
store
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------- LC7 d0
| +------- LC10 d2
| | +----- LC11 d3
| | | +--- LC9 d4
| | | | +- LC8 d5
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'A'
LC | | | | | | A B | Logic cells that feed LAB 'A':
Pin
4 -> * * * * - | * * | <-- ass0
9 -> * * * * - | * * | <-- ass1
8 -> * * * * - | * * | <-- ass2
7 -> * * * * - | * * | <-- ass3
6 -> * * * * - | * * | <-- ass4
5 -> * * * * * | * * | <-- ass5
LC18 -> - - - - * | * - | <-- ~2917~1
LC19 -> - - - - * | * - | <-- ~2917~2
LC20 -> - - - * - | * - | <-- ~3106~1
LC21 -> - - - * - | * - | <-- ~3106~2
LC22 -> - - * - - | * - | <-- ~3295~1
LC23 -> - - * - - | * - | <-- ~3295~2
LC24 -> - * - - - | * - | <-- ~3484~1
LC25 -> - * - - - | * - | <-- ~3484~2
LC31 -> * - - - - | * - | <-- ~3862~1
LC32 -> * - - - - | * - | <-- ~3862~2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\bfsk\store.rpt
store
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC28 d1
| +----------------------------- LC27 d6
| | +--------------------------- LC26 d7
| | | +------------------------- LC17 ~2728~1
| | | | +----------------------- LC18 ~2917~1
| | | | | +--------------------- LC19 ~2917~2
| | | | | | +------------------- LC20 ~3106~1
| | | | | | | +----------------- LC21 ~3106~2
| | | | | | | | +--------------- LC22 ~3295~1
| | | | | | | | | +------------- LC23 ~3295~2
| | | | | | | | | | +----------- LC24 ~3484~1
| | | | | | | | | | | +--------- LC25 ~3484~2
| | | | | | | | | | | | +------- LC29 ~3673~1
| | | | | | | | | | | | | +----- LC30 ~3673~2
| | | | | | | | | | | | | | +--- LC31 ~3862~1
| | | | | | | | | | | | | | | +- LC32 ~3862~2
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC17 -> - * - - - - - - - - - - - - - - | - * | <-- ~2728~1
LC29 -> * - - - - - - - - - - - - - - - | - * | <-- ~3673~1
LC30 -> * - - - - - - - - - - - - - - - | - * | <-- ~3673~2
Pin
4 -> * * * * * * * * * * * * * * * * | * * | <-- ass0
9 -> * * * * * * * * * * * * * * * * | * * | <-- ass1
8 -> * * * * * * * * * * * * * * * * | * * | <-- ass2
7 -> * * * * * * * * * * * * * * * * | * * | <-- ass3
6 -> * * * * * * * * * * * * * * * * | * * | <-- ass4
5 -> * * * * * - * * * * * * * * * * | * * | <-- ass5
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\bfsk\store.rpt
store
** EQUATIONS **
ass0 : INPUT;
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