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<H2>A Color Vision System for Embedded Robotics Applications</H2></CENTER>
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<H4>Verilog FPGA DJ_TOP.V:
<P>Changes in Blue/Bold</H4></CENTER>
<P><PRE>
////////////////////////////////////////////////////////////////////
//
// DJ's video FPGA
//
////////////////////////////////////////////////////////////////////
// Copyright (C), Kenneth Y Maxon Sept, 2004.
module dj_vid_top(
input wire [17:0] proc_addr,
inout wire [7:0] proc_data,
input wire proc_rw,
output wire proc_irq,
input wire proc_cs,
input wire sys_clock,
output wire test_led,
inout wire [14:0] ram_data_io,
output wire [19:1] ram_addr,
output wire ram_we,
output wire ram_oe,
output wire ram_ce,
output wire [14:0] disp_data,
output wire disp_hsync,
output wire disp_vsync,
output wire disp_enable,
output wire disp_clk,
input wire video1_llc,
input wire video1_hsync,
input wire video1_vsync,
input wire [14:0] video1_raw
);
parameter DISPLAY_TOP_ADDR = 18'd153600;
parameter LED_ADDRESS = DISPLAY_TOP_ADDR + 18'h00001;
parameter RESET_ADDRESS = DISPLAY_TOP_ADDR + 18'h00002;
parameter DISPLAY_READY = DISPLAY_TOP_ADDR + 18'h00003;
parameter DISPLAY_STATUS = DISPLAY_TOP_ADDR + 18'h00004;
parameter BEGIN_CAP = DISPLAY_TOP_ADDR + 18'h00005;
parameter CLEAR_FIFO_ERROR = DISPLAY_TOP_ADDR + 18'h00006;
parameter VIDEO1_RED_UPPER = DISPLAY_TOP_ADDR + 18'h00007;
parameter VIDEO1_RED_LOWER = DISPLAY_TOP_ADDR + 18'h00008;
parameter VIDEO1_GREEN_UPPER = DISPLAY_TOP_ADDR + 18'h00009;
parameter VIDEO1_GREEN_LOWER = DISPLAY_TOP_ADDR + 18'h0000A;
parameter VIDEO1_BLUE_UPPER = DISPLAY_TOP_ADDR + 18'h0000B;
parameter VIDEO1_BLUE_LOWER = DISPLAY_TOP_ADDR + 18'h0000C;
parameter BLOBX1 = DISPLAY_TOP_ADDR + 18'h0000D;
parameter BLOBX2 = DISPLAY_TOP_ADDR + 18'h0000E;
parameter BLOBX3 = DISPLAY_TOP_ADDR + 18'h0000F;
parameter BLOBY1 = DISPLAY_TOP_ADDR + 18'h00011;
parameter BLOBY2 = DISPLAY_TOP_ADDR + 18'h00012;
parameter BLOBY3 = DISPLAY_TOP_ADDR + 18'h00013;
parameter VIDEO_CAPTURE_MODE = DISPLAY_TOP_ADDR + 18'h00014;
parameter RANGE_DATA = DISPLAY_TOP_ADDR + 18'h00015;
parameter RANGE_ADDR1 = DISPLAY_TOP_ADDR + 18'h00016;
parameter RANGE_ADDR2 = DISPLAY_TOP_ADDR + 18'h00017;
<B><FONT color=blue>parameter PROC_RESET_READ_PROCESS = DISPLAY_TOP_ADDR + 18'h00018;
parameter PROC_READ_DATA = DISPLAY_TOP_ADDR + 18'h00019;
parameter PROC2_READ_DATA = DISPLAY_TOP_ADDR + 18'h0001A;</FONT></B>
//-------------- local vars
reg test_led_reg;
reg [1:0] qual_counter;
wire qual_data;
wire force_reset;
//-------------- display vars
reg [7:0] proc_data_lower;
wire enable_disp_irq;
wire [17:0] disp_data_get_addr;
//-------------- RAM Scheduler
wire disp_data_get_strb;
wire fifo_error;
reg disp_ping_pong;
//-------------- video1 variables
reg [4:0] video1_red_upper;
reg [4:0] video1_red_lower;
reg [4:0] video1_green_upper;
reg [4:0] video1_green_lower;
reg [4:0] video1_blue_upper;
reg [4:0] video1_blue_lower;
wire [17:0] video1_addr;
wire [14:0] video1_data;
wire video1_store_strb;
wire [3:0] debug_state;
reg [8:0] range_read_address;
wire [7:0] range_data_out;
//-------------- capture module variables
wire blob_capture_done;
wire [23:0] blob1_x_out;
wire [23:0] blob1_y_out;
reg vid_cap_done;
wire data_valid;
wire laser_valid;
reg video_cap_mode;
//-------------- processor data output module variables
wire d_path7,d_path6,d_path5,d_path4,d_path3,d_path2,d_path1,d_path0;
<B><FONT color=blue>//-------------- retrieve data variables
reg [17:0] retrieve_addr;
wire [14:0] retrieve_data;
wire retrieve_data_ready_strb;
wire [14:0] retrieved_data_for_processor;
wire retrieve_fifo_full;
wire adv_ret_state;
reg last_adv_ret_state;
wire advance_retrieved_data;</FONT></B>
//==============================================================
//
// Mains Section:
//
//==============================================================
assign #1 proc_irq = 1'b1;
assign #1 qual_data = ((qual_counter[1:0] == 2'b01) && (~proc_rw));
assign #1 force_reset = (qual_data && (proc_addr[17:0] == RESET_ADDRESS));
always @(posedge sys_clock)
begin
if(proc_cs)
qual_counter[1:0] <= #1 2'b00;
else
qual_counter[1:0] <= qual_counter[1:0] + 2'b01;
end
assign #1 test_led = test_led_reg;
always @(posedge sys_clock)
if((qual_data) && (proc_addr[17:0] == LED_ADDRESS))
test_led_reg <= #1 proc_data[0];
//==============================================================
//
// RAM Scheduler
//
//==============================================================
ram_scheduler my_sched(
.sys_clock(sys_clock),
.force_reset(force_reset),
.proc_data_w({proc_data[6:0],proc_data_lower[7:0]}), //defines 15 not 16 bits
.qual2_data(qual_data && (proc_addr[17:0] < DISPLAY_TOP_ADDR) && ~proc_addr[0]),
.proc_addr(proc_addr[17:1]),
.disp_data_get_addr(disp_data_get_addr[17:0]),
.disp_data_get_strb(disp_data_get_strb),
.disp_data(disp_data[14:0]),
.video1_addr(video1_addr[17:0]),
.video1_data(video1_data[14:0]),
.video1_store_strb(video1_store_strb),
<B><FONT color=blue> .retrieve_addr(retrieve_addr[17:0]),
.retrieve_data(retrieve_data[14:0]),
.retrieve_get_strb(!retrieve_fifo_full),
.retrieve_data_ready_strb(retrieve_data_ready_strb),</FONT></B>
.disp_ping_pong(disp_ping_pong),
.ram_we(ram_we),
.ram_oe(ram_oe),
.ram_ce(ram_ce),
.ram_addr(ram_addr[19:1]),
.ram_data_io(ram_data_io[14:0]),
.fifo_error(fifo_error),
.clear_fifo_error((qual_data) && (proc_addr[17:0] == CLEAR_FIFO_ERROR))
);
always @(posedge sys_clock)
if (force_reset)
disp_ping_pong <= #1 1'b0;
else if ((qual_data) && (proc_addr[17:0] == DISPLAY_READY) && (proc_data[0]))
disp_ping_pong <= #1 ~disp_ping_pong;
<B><FONT color=blue>//==============================================================
//
// DATA RETRIEVER
//
//==============================================================
fifo_33 #(15) ret_datfifo(
.clk(sys_clock),
.rst(qual_data && (proc_addr[17:0] == PROC_RESET_READ_PROCESS)),
.din(retrieve_data[14:0]),
.we(retrieve_data_ready_strb),
.dout(retrieved_data_for_processor[14:0]),
.re(advance_retrieved_data),
.full(retrieve_fifo_full),
.empty()
);
always @(posedge sys_clock)
if (force_reset || ((qual_data) && (proc_addr[17:0] == PROC_RESET_READ_PROCESS)))
retrieve_addr[17:0] <= #1 18'h00000;
else if (retrieve_data_ready_strb)
retrieve_addr[17:0] <= #1 retrieve_addr[17:0] + 18'h00001;
assign #1 adv_ret_state = ((proc_addr[17:0] == PROC2_READ_DATA) && ~proc_cs && proc_rw);
always @(posedge sys_clock)
last_adv_ret_state <= #1 adv_ret_state;
assign #1 advance_retrieved_data = (last_adv_ret_state && !adv_ret_state);</FONT></B>
//==============================================================
//
// Display interfaces
//
//==============================================================
always @(posedge sys_clock)
begin
if(force_reset)
proc_data_lower[7:0] <= 8'h00;
else if(qual_data && (proc_addr[17:0] < DISPLAY_TOP_ADDR) && proc_addr[0])
proc_data_lower[7:0] <= #1 proc_data[7:0];
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