📄 fpga_load.htm
字号:
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<!-- saved from url=(0068)http://www.seattlerobotics.org/encoder/200601/article3/FPGA_load.htm -->
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=gb2312">
<META content="MSHTML 6.00.2900.3243" name=GENERATOR></HEAD>
<BODY text=#000000 vLink=#000000 aLink=#0000ff link=#0000b0
bgColor=#008080><BASEFONT face=Arial color=#ffffff>
<CENTER>
<H2>A Color Vision System for Embedded Robotics Applications</H2></CENTER>From
their web site, Xilinx provides several excellent application notes describing
the different algorithms used to configure their FPGAs. The 'C' code to
implement one such algorithm / interface is provided below:
<P>
<CENTER><A
href="http://www.seattlerobotics.org/encoder/200601/article3/index.php#FPGAload">
<H2>Click here to return to article</H2></A></CENTER>
<P>
<TABLE cellPadding=6 align=center background=FPGA_load.files/grid.gif>
<TBODY>
<TR>
<TD><PRE>extern void feed_watchdog(void);
extern void delay_usec(unsigned short times);
extern void delay_msec(unsigned short times);
#define FPGA_PGM 0x0001 /*PP0*/
#define FPGA_INIT 0x0002 /*PP1*/
#define FPGA_CLK 0x0004 /*PP2*/
#define FPGA_DONE 0x0008 /*PP3*/
#define FPGA_DATA 0x0010 /*PP4*/
// the following line maps PADAT to a bank of general purpose IO pins
#define PADAT cf_imm.pp.PADAT
int loadFpgaConfig(void)
{
unsigned short data;
unsigned short value;
unsigned long i;
int j;
cf_imm.pp.PADDR = 0xF5F5; //A 1 configures as output
//bit 0 - PP0, FPGA_PGM, output
//bit 1 - PP1, FPGA_INIT, input
//bit 2 - PP2, FPGA_CLOCK, output
//bit 3 - PP3, FPGA_DONE, input
//bit 4 - PP4, FPGA_DATA, output
//bit 5 - PP5, NC
//bit 6 - PP6, NC
//bit 7 - PP7, Heartbeat LED, output
//bit 8 - PP0, FPGA2_PGM, output
//bit 9 - PP1, FPGA2_INIT, input
//bit 10- PP2, FPGA2_CLOCK, output
//bit 11- PP3, FPGA2_DONE, input
//bit 12- PP4, FPGA2_DATA, output
//bit 13- PP5, NC
//bit 14- PP6, NC
//bit 15- PP7, NC
feed_watchdog();
PADAT = 0x0100; //set /PGM low to start FPGA program sequence
delay_usec(10); //hold low for about 10 usecs
value = FPGA_PGM; //de-asserts /PGM to begin programming
PADAT = value | 0x100;
feed_watchdog();
#ifndef FPGA_SIMULATION
system_usec_timer = 0;
while ((PADAT & FPGA_INIT) == 0)
{
if (system_usec_timer > 500)
{
feed_watchdog();
dprintf("FPGA Config Error: timed out waiting for memory clear\n\r");
return(1);
}
}
#endif
for(i=0;i<FPGADATA_BYTECOUNT;I++) data="fpgadata_Data[i];" clock the drop 0x100; |="FPGA_DATA;}" PADAT="value" only debug delay_usec(1); edge rising on in clocked value 0x100); FPGA_CLK bit output necessary not are writes between delays so 66MHz of a handle can FPGA &="~FPGA_DATA;}" {value else if(data&0x01) { for(j="0;j8;j++)" feed_watchdog();>> 1;
}
}
PADAT = FPGA_PGM | 0x100; //leave /PGM de-asserted
feed_watchdog();
//normally we'd wait for the DONE signal to go high before moving on...
//also, if /INIT is low at this time, we have a programming error.
#ifndef FPGA_SIMULATION
system_usec_timer = 0;
while ((PADAT & FPGA_DONE) == 0)
{
feed_watchdog();
if ((PADAT & FPGA_INIT) == 0)
{
feed_watchdog();
dprintf("FPGA Config Error: INIT indicates bad CRC\n\r");
return (2);
}
if (system_usec_timer > 50000)
{
feed_watchdog();
dprintf("FPGA Config Error: timed out waiting for DONE to go high\n\r");
return (3);
}
}
#endif
feed_watchdog();
return(0);
}
</PRE></TR></TBODY></TABLE>
<P>
<CENTER>
<H1><A
href="http://www.seattlerobotics.org/encoder/200601/article3/index.php#djv"
target=main>Click here to return to
article</CENTER></A></H1></BASEFONT></BODY></HTML>
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -