cis_system.v

可以产生任意分频,任意占空比的程序

 module cis_system(CLK,RESET,LOCK, clk1,sp,tr,light,CLKOP,black,sp1,tr1);

     input CLK ,RESET ;                                                   
     output LOCK,clk1,CLKOP;                                                      
     output   sp, tr,sp1,tr1;                                                            
     output [7:0] light; 
     output black;

     parameter  idle =2'b00 , uart = 2'b01, scan =2'b10 ;
             

     reg   color;
     reg[1:0] state;

   //  wire[1:0]   state_1,state_2;            
   
     wire    CLKOP,clk1;
     wire   [7:0]  light;

     initial begin 
           color =0;
          
           end
   
    clk0  u1(CLK, RESET, CLKOP, LOCK);      //FPGA锁相环产生一个300MHZ频率

    clock u2(CLKOP,clk1,RESET);             // cis work in frequency
                           
    cis_scan  u4(clk1,sp,tr,light,RESET);
                              
 endmodule 
 

 module  clock(CLKOP,clk1,RESET);
   
     input RESET ,CLKOP;                                                   
     output clk1;                                                    
    
                                                     
     parameter  high_time =30;                                                 
     parameter  low_time =30;
  
     reg        clk1;
     reg[10:0]  duty ; 
     reg[10:0]  clkhigh;
     reg[10:0]  clklow ;                                                     
                                  // reg[7:0]  vol_ref_1;                                                                                
  
 always  @(posedge CLKOP or posedge RESET )       //product clk1 ,
      begin
       if(RESET)
           begin 
             duty =0;
             clkhigh =high_time;
             clklow  = low_time;
             clk1=0;
           end  else  
           begin 
                   case (duty)

                   clklow:    clk1 =~clk1;
                  
                   clkhigh:      
                              begin
                                clk1 =~clk1;
                                duty =0;
                              end
 
                   default : duty =duty +1;
                  endcase
           end
     end
 endmodule 

 module  cis_scan(clk1,sp,tr,light_ctr,RESET);
    input      clk1,RESET;
    output     sp,tr;
    output [7:0] light_ctr;
  // output [1:0] state;

    parameter  pixel_count=1288 ;                                              
    parameter  color_1      =1;  
    parameter  light_time=20;                                                  
//  parameter  vol_ref   =150;                                                 
    parameter  spi_width =6;                                                 
    parameter  delay_time=3;                                                   
    parameter  preclock = 10; 
    parameter  uart = 2'b01, scan =2'b10 ;

     reg     color;
     reg     sp;
     reg     tr;
     reg[7:0]  light_ctr;
     reg[16:0] t0;
     reg[16:0] t1;
     reg[16:0] t2;
     reg[16:0] t3;
     reg[16:0] t4;
     reg[16:0] clk_count;
     reg[1:0] state;
     reg[3:0] light_count;
     reg[3:0] count;
 
    
      initial begin
                                //  vol_ref_1 = 150;
       
       clk_count = 0;
       count =4'd12;
       state =2'b00; 
       light_count =0;                                       
       sp = 0;
       tr = 0;                                                    
       clk_count[16:0] = 0;
       t0[16:0] = preclock;
       t1[16:0] = preclock+light_time;
       t2[16:0] = preclock+spi_width;
       t3[16:0] = preclock + pixel_count;
       t4[16:0] = preclock +pixel_count+delay_time; 
     end   

always @(posedge clk1 or posedge RESET)   //contrl  cis work;
    begin 
      if(RESET)
           begin
            sp=0;
            tr=0;
            clk_count = 0;
            end else  begin
         color =color_1;
       if(color==1)
            begin
              count =12;
             light_ctr =8'd1;
            end else begin
               count =4;
              light_ctr =8'd01010101;
            end
                                                                
     case (clk_count)                    //  if( clk_count ==preclock )
     
      t0:     
            begin
             sp =1;
             tr =1;
             light_ctr[7:0] ={light_ctr[6:0],light_ctr[7]};          
            end 

     t1: light_ctr[7:0] = {light_ctr[6:0],light_ctr[7]};
     t2: sp =0;
     t3: tr=0;
     t4: begin
            clk_count =0;
            if(light_count ==count)
              begin
              light_count=0;
           //   state = uart;
              end else begin
                   light_count=light_count+1;
              //     state = scan;
                        end
          end
     default :clk_count = clk_count+1; 

   endcase
  end
 end   
endmodule