untitled.syn

可以产生任意分频,任意占空比的程序

JDF B
// Created by Version 6.1 
PROJECT Untitled
DESIGN untitled Normal
DEVKIT LFXP3C-3P208C
ENTRY Schematic/Verilog HDL
MODULE cis_system.v
MODSTYLE clock Normal
MODSTYLE cis_system Normal
TESTFIXTURE cis_system cis_test.v
MODSTYLE cis_scan Normal
MODULE clk0.v
MODSTYLE clk0 Normal
SYNTHESIS_TOOL Synplify
TOPMODULE cis_system