clk0.v

可以产生任意分频,任意占空比的程序

/* Verilog netlist generated by SCUBA ispLever_v61_PROD_Build (37) */
/* Module Version: 3.2 */
/* C:\ispTOOLS6_1\ispfpga\bin\nt\scuba.exe -w -n clk0 -lang verilog -synth synplify -arch mg5g00 -type pll -fin 50 -fclkop 300 -fclkop_tol 0.0 -delay_cntl STATIC -fdel 0 -fb_mode CLOCKTREE -noclkos -noclkok -e  */
/* Thu Aug 09 10:16:35 2007 */


`timescale 1 ns / 1 ps
module clk0 (CLK, RESET, CLKOP, LOCK);
    input CLK;
    input RESET;
    output CLKOP;
    output LOCK;

    wire CLK_t;

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    // synopsys translate_off
    defparam PLLBInst_0.DELAY_CNTL = "STATIC" ;
    defparam PLLBInst_0.FDEL = "0" ;
    defparam PLLBInst_0.DUTY = "4" ;
    defparam PLLBInst_0.PHASEADJ = "0" ;
    defparam PLLBInst_0.CLKOK_DIV = "2" ;
    defparam PLLBInst_0.CLKOP_DIV = "2" ;
    defparam PLLBInst_0.CLKFB_DIV = "6" ;
    defparam PLLBInst_0.CLKI_DIV = "1" ;
    // synopsys translate_on
    EHXPLLB PLLBInst_0 (.CLKI(CLK_t), .CLKFB(CLKOP_t), .RST(RESET), .DDAMODE(scuba_vlo), 
        .DDAIZR(scuba_vlo), .DDAILAG(scuba_vlo), .DDAIDEL0(scuba_vlo), .DDAIDEL1(scuba_vlo), 
        .DDAIDEL2(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOK(), .LOCK(LOCK), 
        .DDAOZR(), .DDAOLAG(), .DDAODEL0(), .DDAODEL1(), .DDAODEL2())
             /* synthesis DELAY_CNTL="STATIC" */
             /* synthesis FDEL="0" */
             /* synthesis DUTY="4" */
             /* synthesis PHASEADJ="0" */
             /* synthesis FB_MODE="CLOCKTREE" */
             /* synthesis FREQUENCY_PIN_CLKOS="300.000000" */
             /* synthesis FREQUENCY_PIN_CLKOP="300.000000" */
             /* synthesis FREQUENCY_PIN_CLKI="50.000000" */
             /* synthesis FREQUENCY_PIN_CLKOK="50.000000" */
             /* synthesis CLKOK_DIV="2" */
             /* synthesis CLKOP_DIV="2" */
             /* synthesis CLKFB_DIV="6" */
             /* synthesis CLKI_DIV="1" */
             /* synthesis FIN="50.000000" */;

    assign CLKOP = CLKOP_t;
    assign CLK_t = CLK;


    // exemplar begin
    // exemplar attribute PLLBInst_0 DELAY_CNTL STATIC
    // exemplar attribute PLLBInst_0 FDEL 0
    // exemplar attribute PLLBInst_0 DUTY 4
    // exemplar attribute PLLBInst_0 PHASEADJ 0
    // exemplar attribute PLLBInst_0 FB_MODE CLOCKTREE
    // exemplar attribute PLLBInst_0 FREQUENCY_PIN_CLKOS 300.000000
    // exemplar attribute PLLBInst_0 FREQUENCY_PIN_CLKOP 300.000000
    // exemplar attribute PLLBInst_0 FREQUENCY_PIN_CLKI 50.000000
    // exemplar attribute PLLBInst_0 FREQUENCY_PIN_CLKOK 50.000000
    // exemplar attribute PLLBInst_0 CLKOK_DIV 2
    // exemplar attribute PLLBInst_0 CLKOP_DIV 2
    // exemplar attribute PLLBInst_0 CLKFB_DIV 6
    // exemplar attribute PLLBInst_0 CLKI_DIV 1
    // exemplar attribute PLLBInst_0 FIN 50.000000
    // exemplar end

endmodule