and2a.tan.qmsg

来自「EDA课程设计,简单的EDA编程,包括计数器」· QMSG 代码 · 共 6 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Sep 14 10:29:39 2008 " "Info: Processing started: Sun Sep 14 10:29:39 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off and2a -c and2a --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off and2a -c and2a --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "b c 8.929 ns Longest " "Info: Longest tpd from source pin \"b\" to destination pin \"c\" is 8.929 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns b 1 PIN PIN_AA12 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AA12; Fanout = 1; PIN Node = 'b'" {  } { { "d:/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/win/TimingClosureFloorplan.fld" "" "" { b } "NODE_NAME" } } { "or2a.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/我的文档/ex1/or2a.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.673 ns) + CELL(0.366 ns) 5.126 ns c~0 2 COMB LC_X25_Y1_N2 1 " "Info: 2: + IC(3.673 ns) + CELL(0.366 ns) = 5.126 ns; Loc. = LC_X25_Y1_N2; Fanout = 1; COMB Node = 'c~0'" {  } { { "d:/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/win/TimingClosureFloorplan.fld" "" "4.039 ns" { b c~0 } "NODE_NAME" } } { "or2a.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/我的文档/ex1/or2a.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.116 ns) + CELL(2.687 ns) 8.929 ns c 3 PIN PIN_AB12 0 " "Info: 3: + IC(1.116 ns) + CELL(2.687 ns) = 8.929 ns; Loc. = PIN_AB12; Fanout = 0; PIN Node = 'c'" {  } { { "d:/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/win/TimingClosureFloorplan.fld" "" "3.803 ns" { c~0 c } "NODE_NAME" } } { "or2a.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/我的文档/ex1/or2a.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.140 ns ( 46.37 % ) " "Info: Total cell delay = 4.140 ns ( 46.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.789 ns ( 53.63 % ) " "Info: Total interconnect delay = 4.789 ns ( 53.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/win/TimingClosureFloorplan.fld" "" "8.929 ns" { b c~0 c } "NODE_NAME" } } { "d:/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/win/Technology_Viewer.qrui" "8.929 ns" { b b~out0 c~0 c } { 0.000ns 0.000ns 3.673ns 1.116ns } { 0.000ns 1.087ns 0.366ns 2.687ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Sep 14 10:29:40 2008 " "Info: Processing ended: Sun Sep 14 10:29:40 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}