dds.txt

硬件描述语言实现的DDS和dds的测试程序

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    07:20:56 09/09/2007 
-- Design Name: 
-- Module Name:    main - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity main is
    Port ( clk : in  STD_LOGIC;
           data_in : in  STD_LOGIC_VECTOR (13 downto 0);
           data_out : out  STD_LOGIC_VECTOR (7 downto 0));
end main;

architecture Behavioral of main is

    type wave is array (integer range<>) of std_logic_vector(7 downto 0) ;
    constant wave1: wave(255 downto 0) :=(
	 x"7F" , x"82" , x"85" , x"88" , x"8B" , x"8E" , x"91" , x"94" ,
    x"97" , x"9A" , x"9D" , x"A0" , x"A3" , x"A6" , x"A9" , x"AC" ,
	 x"AF" , x"B2" , x"B5" , x"B8" , x"BA" , x"BD" , x"C0" , x"C2" ,
	 x"C5" , x"C8" , x"CA" , x"CD" , x"CF" , x"D1" , x"D4" , x"D6" ,
	 x"D8" , x"DA" , x"DD" , x"DF" , x"E1" , x"E3" , x"E5" , x"E6" ,
	 x"E8" , x"EA" , x"EB" , x"ED" , x"EF" , x"F0" , x"F1" , x"F3" , 
	 x"F4" , x"F5" , x"F6" , x"F7" , x"F8" , x"F9" , x"FA" , x"FA" ,
	 x"FB" , x"FC" , x"FC" , x"FD" , x"FD" , x"FD" , x"FD" , x"FD" , 
	 x"FE" , x"FD" , x"FD" , x"FD" , x"FD" , x"FD" , x"FC" , x"FC" ,
	 x"FB" , x"FA" , x"FA" , x"F9" , x"F8" , x"F7" , x"F6" , x"F5" ,
	 x"F4" , x"F3" , x"F1" , x"F0" , x"EF" , x"ED" , x"EB" , x"EA" ,
	 x"E8" , x"E6" , x"E5" , x"E3" , x"E1" , x"DF" , x"DD" , x"DA" ,
	 x"D8" , x"D6" , x"D4" , x"D1" , x"CF" , x"CD" , x"CA" , x"C8" ,
	 x"C5" , x"C2" , x"C0" , x"BD" , x"BA" , x"B8" , x"B5" , x"B2" ,
	 x"AF" , x"AC" , x"A9" , x"A6" , x"A3" , x"A0" , x"9D" , x"9A" ,
	 x"97" , x"94" , x"91" , x"8E" , x"8B" , x"88" , x"85" , x"82" , 
	 x"7F" , x"7B" , x"78" , x"75" , x"72" , x"6F" , x"6C" , x"69" , 
	 x"66" , x"63" , x"60" , x"5D" , x"5A" , x"57" , x"54" , x"51" , 
	 x"4E" , x"4B" , x"48" , x"45" , x"43" , x"40" , x"3D" , x"3B" ,
	 x"38" , x"35" , x"33" , x"30" , x"2E" , x"2C" , x"29" , x"27" ,
	 x"25" , x"23" , x"20" , x"1E" , x"1C" , x"1A" , x"18" , x"17" ,
	 x"15" , x"13" , x"12" , x"10" , x"0E" , x"0D" , x"0C" , x"0A" , 
	 x"09" , x"08" , x"07" , x"06" , x"05" , x"04" , x"03" , x"03" ,
	 x"02" , x"01" , x"01" , x"00" , x"00" , x"00" , x"00" , x"00" ,
	 x"00" , x"00" , x"00" , x"00" , x"00" , x"00" , x"01" , x"01" ,
	 x"02" , x"03" , x"03" , x"04" , x"05" , x"06" , x"07" , x"08" ,
	 x"09" , x"0A" , x"0C" , x"0D" , x"0E" , x"10" , x"12" , x"13" ,
	 x"15" , x"17" , x"18" , x"1A" , x"1C" , x"1E" , x"20" , x"23" ,
	 x"25" , x"27" , x"29" , x"2C" , x"2E" , x"30" , x"33" , x"35" ,
	 x"38" , x"3B" , x"3D" , x"40" , x"43" , x"45" , x"48" , x"4B" ,
	 x"4E" , x"51" , x"54" , x"57" , x"5A" , x"5D" , x"60" , x"63" , 
	 x"66" , x"69" , x"6C" , x"6F" , x"72" , x"75" , x"78" , x"7B" 
	 
	 );
  
  
signal fre:std_logic_vector(31 downto 0):=x"00000000";
signal fre_con:std_logic_vector(16 downto 0):='0'& x"0000"; 
signal sum : std_logic_vector(17 downto 0):=(others=>'0');
constant para :std_logic_vector(15 downto 0):=x"C350";   -- 50MHz 
  
	COMPONENT devider
	PORT(
		clk : IN std_logic;
		data_in : IN std_logic_vector(31 downto 0);
		data_in_d : IN std_logic_vector(15 downto 0);          
		data_out : OUT std_logic_vector(16 downto 0)
		);
	END COMPONENT;


  
begin

  process(clk)
  
  
   begin
	    
	  if rising_edge(clk) then 
	    fre(31 downto 18) <= data_in;
     
       sum <= sum +fre_con;

       data_out <= wave1(CONV_INTEGER(sum(17 downto 10)));
	  end if;
	end process;  
		
	Inst_devider: devider PORT MAP(
		clk => clk,
		data_in => fre,
		data_in_d => para,
		data_out => fre_con
	);  



end Behavioral;






//////////////////////////////////////////////////////////


--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   08:01:53 09/16/2007
-- Design Name:   main
-- Module Name:   C:/Xilinx/test/work6/dds/test_for_dds.vhd
-- Project Name:  dds
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: main
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY test_for_dds_vhd IS
END test_for_dds_vhd;

ARCHITECTURE behavior OF test_for_dds_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT main
	PORT(
		clk : IN std_logic;
		data_in : IN std_logic_vector(13 downto 0);          
		data_out : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL data_in :  std_logic_vector(13 downto 0) := (others=>'0');

	--Outputs
	SIGNAL data_out :  std_logic_vector(7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: main PORT MAP(
		clk => clk,
		data_in => data_in,
		data_out => data_out
	);

   clk <= not clk after 5 ns;

	tb : PROCESS
	BEGIN
     
		-- Wait 100 ns for global reset to finish
		wait for 100 ns;
       data_in <="00"&x"0f0";
		-- Place stimulus here

		wait; -- will wait forever
	END PROCESS;

END;