count_10.vhd

来自「用VHDL语言描述的用锁存器」· VHDL 代码 · 共 26 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT_10 IS
   PORT(CLK ,EA,RST : IN STD_LOGIC;
        Q_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END;
ARCHITECTURE BEV OF COUNT_10 IS
SIGNAL C_COUNT : STD_LOGIC_VECTOR(3 DOWNTO 0); 
BEGIN
  PROCESS(CLK,EA,RST)
  BEGIN
    IF(RST = '1' ) THEN
       C_COUNT <= "0000";
    ELSIF(EA = '1') THEN
        IF ( CLK'EVENT AND CLK = '1') THEN
           IF (C_COUNT = "1001") THEN
               C_COUNT <= "0000";
           ELSE
           C_COUNT <= C_COUNT + 1;
           END IF;
        END IF;
    END IF;
  END PROCESS;
  Q_OUT <= C_COUNT;
END;