singt.tan.qmsg

用VHDL语言描述的用锁存器

{ "Info" "ITDB_FULL_TCO_RESULT" "in_clk sin_out\[0\] rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|q_a\[0\] 6.798 ns memory " "Info: tco from clock \"in_clk\" to destination pin \"sin_out\[0\]\" through memory \"rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|q_a\[0\]\" is 6.798 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "in_clk pll_w:inst1\|altpll:altpll_component\|_clk0 -2.054 ns + " "Info: + Offset between input clock \"in_clk\" and output clock \"pll_w:inst1\|altpll:altpll_component\|_clk0\" is -2.054 ns" {  } { { "singt.bdf" "" { Schematic "E:/singt/singt.bdf" { { 384 -104 64 400 "in_clk" "" } } } } { "altpll.tdf" "" { Text "d:/altera/61/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll_w:inst1\|altpll:altpll_component\|_clk0 source 2.445 ns + Longest memory " "Info: + Longest clock path from clock \"pll_w:inst1\|altpll:altpll_component\|_clk0\" to source memory is 2.445 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll_w:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 50 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 50; CLK Node = 'pll_w:inst1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll_w:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/61/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.737 ns) + CELL(0.708 ns) 2.445 ns rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|q_a\[0\] 2 MEM M4K_X19_Y11 1 " "Info: 2: + IC(1.737 ns) + CELL(0.708 ns) = 2.445 ns; Loc. = M4K_X19_Y11; Fanout = 1; MEM Node = 'rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|q_a\[0\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.445 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_ps21.tdf" "" { Text "E:/singt/db/altsyncram_ps21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.708 ns ( 28.96 % ) " "Info: Total cell delay = 0.708 ns ( 28.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.737 ns ( 71.04 % ) " "Info: Total interconnect delay = 1.737 ns ( 71.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.445 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.445 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } { 0.000ns 1.737ns } { 0.000ns 0.708ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_ps21.tdf" "" { Text "E:/singt/db/altsyncram_ps21.tdf" 40 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.757 ns + Longest memory pin " "Info: + Longest memory to pin delay is 5.757 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.104 ns) 0.104 ns rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|q_a\[0\] 1 MEM M4K_X19_Y11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X19_Y11; Fanout = 1; MEM Node = 'rom_sin:inst\|altsyncram:altsyncram_component\|altsyncram_ps21:auto_generated\|q_a\[0\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_ps21.tdf" "" { Text "E:/singt/db/altsyncram_ps21.tdf" 40 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.545 ns) + CELL(2.108 ns) 5.757 ns sin_out\[0\] 2 PIN PIN_208 0 " "Info: 2: + IC(3.545 ns) + CELL(2.108 ns) = 5.757 ns; Loc. = PIN_208; Fanout = 0; PIN Node = 'sin_out\[0\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.653 ns" { rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] sin_out[0] } "NODE_NAME" } } { "singt.bdf" "" { Schematic "E:/singt/singt.bdf" { { 232 744 920 248 "sin_out\[9..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.212 ns ( 38.42 % ) " "Info: Total cell delay = 2.212 ns ( 38.42 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.545 ns ( 61.58 % ) " "Info: Total interconnect delay = 3.545 ns ( 61.58 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.757 ns" { rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] sin_out[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.757 ns" { rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] sin_out[0] } { 0.000ns 3.545ns } { 0.104ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "2.445 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "2.445 ns" { pll_w:inst1|altpll:altpll_component|_clk0 rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] } { 0.000ns 1.737ns } { 0.000ns 0.708ns } "" } } { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.757 ns" { rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] sin_out[0] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "5.757 ns" { rom_sin:inst|altsyncram:altsyncram_component|altsyncram_ps21:auto_generated|q_a[0] sin_out[0] } { 0.000ns 3.545ns } { 0.104ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." {  } {  } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "100 " "Info: Allocated 100 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 14 09:57:47 2009 " "Info: Processing ended: Tue Apr 14 09:57:47 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}